Research Group Activities - Integrated Circuits
The work in this field started essentially with an interest in IC testing
due to some connection with the area of device reliability.
At the beginning, the research was focussed on fault modeling and
simulation (for the type of failures of importance for CMOS
technologies) and innovative Design-for-Testability techniques
aimed at detecting non-stuck-at faults (in particular bridgings).
From this type of activity, the research of the Group in IC testing
progressively expanded beyond the electrical level,
to include also more theoretical topics. The first analytical theory of
signature analysis testing is among the results of greater interest from
this point of view.
Because of obvious interactions among circuit design,
test and architectures, later the work was extended to other aspects
of modern ICs, and significant results have been
obtained on: Self-checking and Fault-Tolerant architectures, CMOS power
simulation and modeling, synthesis for low power,
adjustable analog circuits (exploiting Non-Volatile Memories).
In this field too, experiments have played a relevant role.
In particular, a number of test chips have been designed, realized and
tested in order to verify theoretical and original ideas.