Fault modeling

M. Favalli, P. Olivo, M. Damiani, and B. Riccò,
`` Fault Simulation of Unconventional Faults in CMOS ICs'',
IEEE Transaction on CAD, vol. 10, pp. 677 -- 682, 1991.

M. Ambanelli, M. Favalli, M. Dalpasso, P. Olivo, and B. Riccó,
`` Fault Simulation of Multiple Faults in PLAs'',
in IEEE CompEuro, pp. 229 -- 232, 1991.

M. Favalli, P. Olivo, and B. Riccò,
`` A Probabilistic Fault Model for Analog Faults in CMOS Circuits'',
in IEEE European Conference on Design Automation, pp. 85 -- 88, 1991.

M. Ambanelli, M. Favalli, P. Olivo, and B. Riccò,
`` Detection of PLA Multiple Crosspoints Faults'',
in IEEE European Conference on Design Automation, pp. 80 -- 84, 1991.

B. Riccò, M. Favalli, and P. Olivo,
`` Comprehensive Fault Modeling and Simulation in CMOS ICs'',
in IEEE CompEuro, pp. 778 -- 785, 1991. invited.

M. Favalli, P. Olivo, and B. Riccò,
`` A Probabilistic Fault Model for ``Analog'' Faults in Digital CMOS Circuits'',
IEEE Transaction on CAD, vol. 11, pp. 1459 -- 1462, 1992.

M. Favalli, P. Olivo, and B. Riccò,
`` Dynamic Effects in the Detection of Bridging Faults in CMOS ICs'',
Jou. of Electronic Testing: Theory and Application, vol. 3, pp. 197 -- 205, 1992.

M. Favalli, P. Olivo, and B. Riccò,
`` Dynamic Effects in the Detection of Bridging Faults in CMOS ICs'',
Presented at IEEE European DFT Workshop, June 1992.

M. Favalli, M. Dalpasso, P. Olivo, and B. Riccò,
`` Analysis of Steady State Detection of Resistive Bridging Faults in BiCMOS Digital ICs'',
in Proc. of IEEE Int. Test Conf., pp. 466 -- 475, 1992.

M. Favalli, M. Dalpasso, P. Olivo, and B. Riccò,
`` Analysis of Dynamic Effects of Resistive Bridging Faults in BiCMOS Digital ICs'',
in Proc. of IEEE Int. Test Conf., pp. 865 -- 873, 1993.

M. Favalli, M. Dalpasso, P. Olivo, and B. Riccò,
`` Analysis of Resistive Bridging Fault Detection in BiCMOS Digital ICs'',
IEEE Transaction on VLSI Systems, vol. 1, no. 3, pp. 342 -- 355, 1993.

M. Favalli, M. Dalpasso, P. Olivo, and B. Riccò,
`` Modeling of broken connection faults in CMOS ICs'',
in IEEE European Conference on Design Automation, pp. 159 -- 164, 1994.

Fault simulation

M. Favalli, P. Olivo, F. Somenzi, and B. Riccò,
`` Fault Simulation for General FCMOS ICs'',
Jou. of Electronic Testing: Theory and Application, vol. 2, pp. 181 -- 190, 1991.

M. Favalli, P. Olivo, and B. Riccò,
`` A Novel Critical Path Heuristic for Fast Fault Grading'',
IEEE Transaction on CAD, vol. 10, pp. 544 -- 548, 1991.

M. Dalpasso, M. Favalli, P. Olivo, and B. Riccò,
`` Switch-Level Fault Simulation by Critical Path Tracing'',
in Proc. of IEEE Eur. Test Conf., pp. 181 -- 190, 1991.

M. Dalpasso, M. Favalli, P. Olivo, and B. Riccò,
`` Parametric Bridging Fault Characterization for the Fault Simulation of Library-Based ICs'',
in Proc. of IEEE Int. Test Conf., pp. 486 -- 495, 1992.

M. Dalpasso, M. Favalli, P. Olivo, and B. Riccò,
`` Fault Simulation of Parametric Bridging Faults in CMOS ICs'',
IEEE Transaction on CAD, vol. 12, no. 9, pp. 1403--1410, 1993.

M. Dalpasso, M. Favalli, P. Olivo, and B. Riccò,
`` Influence of ic synthesis on the random pattern testability of parametric bridging faults'',
in Proc. of IEEE Eur. Test Conf., pp. 398 -- 407, 1993.

M. Dalpasso, M. Favalli, P. Olivo, and J. Teixeira,
`` Realistic testability estimates for CMOS IC's'',
IEE Electronic Letters, vol. 30, no. 19, pp. 1593 -- 1595, 1994.

M. Dalpasso, M. Favalli, and P. Olivo,
`` Test pattern generation for Iddq: Increasing test quality'',
in IEEE European Desingn and Test Conference, pp. 304 -- 309, 1995.

M. Dalpasso, M. Favalli, and P. Olivo,
`` Correlation between Iddq Testing Quality and Sensor Accuracy'',
in IEEE European Desingn and Test Conference, pp. 568 -- 572, 1995.

Aliasing in Signature Analysis

M. Damiani, P. Olivo, M. Favalli, and B. Riccò,
`` Aliasing Errors in Signature Analysis Testing of Integrated Circuits'',
in Proc. of IEEE Int. Conf. On Computer Design, pp. 458 -- 461, 1988.

M. Damiani, P. Olivo, M. Favalli, and B. Riccò,
`` An Analytical Model for the Aliasing Probability in Signature Analysis Testing'',
IEEE Transaction on CAD, vol. 8, pp. 1133 -- 1144, 1989.

M. Damiani, P. Olivo, M. Favalli, S. Ercolani, and B. Riccò,
`` Aliasing in Signature Analysis Testing with Multiple-Input Shift-Registers'',
in Proc. of IEEE Eur. Test Conf., pp. 346 -- 352, 1989.

P. Olivo, M. Damiani, and B. Riccò,
``On the Design of Multiple-Input Shift-Registers for Signature Analysis Testing'',
in Proc. of IEEE Int. Test Conf. (ITC), p. 936, 1989

M. Damiani, P. Olivo, M. Favalli, S. Ercolani, and B. Riccò,
`` Aliasing in Signature Analysis Testing with Multiple-Input Shift-Registers'',
IEEE Transaction on CAD, vol. 12, pp. 1344 -- 1353, 1990.

M. Damiani, P. Olivo, and B. Riccò,
``Analysis and Design of Linear Finite State Machine for Signature Analysis Testing'',
IEEE Trans. on Computers, Vol. C-40, pp. 1034-1045, 1991

Testability Measures

S. Ercolani, M. Favalli, M. Damiani, P. Olivo, and B. Riccò,
`` Estimate of Signal Probability in Combinational Networks'',
in Proc. of IEEE Eur. Test Conf., pp. 132 -- 138, 1989.

S. Ercolani, M. Favalli, P. Olivo, M. Damiani, and B. Riccò,
`` Improved Testability Evaluation in Combinational Logic Networks'',
in Proc. of IEEE Int. Conf. On Computer Design, pp. 352 -- 355, 1989.

M. Favalli, S. Ercolani, M. Dalpasso, P. Olivo, and B. Riccó,
`` Weighted Pseudorandom Generation for Built-In Self-Test'',
in IEEE CompEuro, pp. 572 -- 574, 1991.

S. Ercolani, M. Favalli, M. Damiani, P. Olivo, and B. Riccò,
`` Testability Measures in Pseudorandom Testing'',
IEEE Transaction on CAD, vol. CAD-11, pp. 794 -- 800, 1992.

M. Favalli, P. Olivo, and B.Riccò,
`` Testability Measures Combining Probabilistic and Sampling Techniques'',
in IEEE European Conference on Design Automation, pp. 425 -- 431, 1993.

DFT for CMOS ICs

M. Favalli, P. Olivo, M. Damiani, and B. Riccò,
`` CMOS Design for Improved IC Testability'',
in Proc. of IEEE Int. Test Conf., p. 934, 1989.

M. Favalli, P. Olivo, and B. Riccò,
`` A Circuit for the Detection of Delay Faults in CMOS ICs'',
presented at the European DFT Workshop (Segovia), 1990.

M. Favalli, P. Olivo, M. Damiani, and B. Riccò,
`` Novel Design for Testability Schemes for CMOS ICs'',
IEEE J. of Solid State Circuit, vol. 25, pp. 1239 -- 1246, 1990.

M. Lanzoni, M. Favalli, P. Olivo, and B. Riccò,
`` An Experimental Study of Testing Techniques for Bridging and Transistor Stuck-on Faults'',
Presented at IEEE European DFT Workshop, June 1992.

M. Lanzoni, M. Favalli, P. Olivo, and B. Riccò,
`` An Experimental Study of Testing Techniques for Bridging and Transistor Stuck-on Faults'',
IEEE J. of Solid State Circuit, vol. 28, no. 6, pp. 686 -- 690, 1993.

M. Lanzoni, M. Favalli, P. Olivo, and B. Riccò,
`` An implementation of CMOS design for testability techniques for non stuck-at faults'',
in IEEE Int. Conf. on Microelectronics Test Structures, pp. 95 -- 99, 1993.

M. Favalli, B. Riccò, and L. Penza,
`` A novel DFT technique for critical bridging faults in CMOS and BiCMOS ICs'',
in IEEE European Desingn and Test Conference, pp. 568 -- 572, 1995.

M. Favalli and B. Riccò,
`` A novel DFT technique for Comprehensive Testing of CMOS buff ers'',
Alta Frequenza, vol. 7, no. 2, pp. 78 -- 80, 1995.

Self-Checking Circuits

C. Metra, M. Favalli, P. Olivo, and B. Riccò,
`` CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults'',
Presented at IEEE European DFT Workshop, June 1992.

C. Metra, M. Favalli, P. Olivo, and B. Riccò,
`` CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults'',
in Proc. of IEEE Int. Test Conf., pp. 948 -- 957, 1992.

C. Metra, M. Favalli, P. Olivo, and B. Riccò,
`` Testing of resistive bridging and transistor stuck-on faults in CMOS flip-flops'',
in Proc. of IEEE Eur. Test Conf., pp. 530 -- 531, 1993.

C. Metra, M. Favalli, P. Olivo, and B. Riccò,
`` A highly testable 1-out-of-3 CMOS checker'',
in IEEE Int. Worlshop on Defect and Fault Tolerance in VLSI Systems, pp. 279 -- 286, 1993.

C. Metra, M. Favalli, P. Olivo, and B. Riccò,
`` Design rules for CMOS self checking circuits with parametric faults in the functional block'',
in IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 271 -- 278, 1993.

C. Metra, M. Favalli, and B. Riccò,
`` Novel 1-out-of-n CMOS checkers'',
IEE Electronic Letters, vol. 30, no. 17, pp. 1398 -- 1400, 1994.

C. Metra, M. Favalli, and B. Riccò,
`` CMOS Self-Checking Circuits with Faulty Sequential Fun ctional Blocks'',
in IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 133 -- 141, 1994.

C. Metra, M. Favalli, and B. Riccò,
`` Highly Testable and Compact 1-out-of-n CMOS Checkers'',
in Int. Work. on Defect and Fault Tolerance in VLSI Systems, pp. 142 -- 150, 1994.

C. Metra, M. Favalli, P. Olivo, and B. Riccò,
`` CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults'',
Jou. of Electronic Testing: Theory and Application, vol. 6, pp. 7 -- 22, 1995.

C. Metra, M. Favalli, and B. Riccó,
`` Novel berger code checker'',
in IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 287 -- 295, 1995.

C. Metra, M. Favalli, and B. Riccó,
`` Design of TSC CMOS checkers for any 1-out-of-n code'',
Journal of Microelectronics System Integration , vol. 3, n. 2, pp. 81 -- 91, 1995.

C. Metra, M. Favalli;,
`` 1-out-of-n dynamic CMOS checker'',
Electronic Letters , pp. 1999 -- 2001, 1995.

M. Favalli and C. Metra,
``Sensing circuit on-line detection o f delay faults'',
IEEE Transaction on VLSI Systems, vol. 4, no.& nbsp;1, pp. 139 - 133, 1996.

C. Metra and J-C. Lo,
" Compact and High Speed Berger Code Checker ",
in Proceedings of IEEE International On-Line Testing Workshop , St. Jean de Luz (France), pp.~144--149, July 8-10, 1996.

C. Metra, M. Favalli, B. Riccò,
" Embedded 1-out-of-3 Checkers with On-Line Testing Ability ",
in Proceedings of IEEE International On-Line Testing Workshop , St. Jean de Luz (France), pp. 136--141, July 8-10, 1996.

C. Metra, M. Favalli, B. Riccò,
" Tree Checkers for Applications with Low Power-Delay Requirements ",
in IEEE Proceedings of The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems , Boston (MA), pp. 213-220, November 6-8, 1996.

C. Metra, M. Favalli, B. Riccò,
" Compact and Highly Testable Error Indicator for Self-Checking Circuits ",
in IEEE Proceedings of The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems , Boston (MA), pp. 204-212, November 6-8, 1996.

Simulation

L. Benini, M. Favalli, P. Olivo, and B.Riccò,
`` A novel approach to cost-effective estimate power dissipation in CMOS ICs'',
in IEEE European Conference on Design Automation, pp. 354 -- 360, 1993.

L. Benini, M. Favalli, and B. Riccò,
`` Analysis of hazard contribution to power dissipation in CMOS ic's'',
in IEEE Int. Workshop on Low Power Design, pp. 27 -- 32, 1994.

M. Favalli and L. Benini,
`` Analysis of glitch power dissipation in CMOS IC's'',
in Int'l Symposium on Low Power Design, pp. 123 -- 128, 1995.

C. Metra, M. Favalli, and B. Riccò,
`` Glitch Power Dissipation Model'',
in Proc. of Power Timing Modeling Optimization Simulation (PATMOS), pp. 175 -- 189, 1995.

M. Favalli and C. Metra,
`` The effect of glitches on CMOS buffer optimization'',
in Power Timing Modeling Simulation Optimization, pp. 202 -- 212, 1995.

Tutorials (in italian)

M. Favalli, P. Olivo, and B. Riccò,
`` Progettazione Orientata al Collaudo di Circuiti Integrati Digitali'',
Alta Frequenza, vol. II, pp. 55 -- 63, 1990.

B. Riccò, M. Favalli, and L. Selmi,
`` Logiche di tipo di BiCMOS'',
Alta Frequenza, vol. III, pp. 25 -- 36, 1991.

M. Favalli and M. Dalpasso,
`` Simulazione di Guasti in Circuiti Integrati Digitali'',
Alta Frequenza, vol. IV, pp. 13 -- 22, 1992.

P. Olivo and M. Favalli, Esercizi di elettronica digitale. Esculapio, 1991.



Michele Favalli
Thu Dec 21 17:24:18 MET 1995