Computer-Aided Testing of Digital ICs

This research activity mainly regards the fault simulation and modeling of unconventional faults in CMOS circuits. Starting from the evidence that the traditional stuck-at fault model is not sufficient to describe all the possible defects in CMOS ICs, we have studied models for [refs.]:
resistive bridging faults in CMOS and BiCMOS circuits;
broken connection faults in CMOS circuits;
based on these models we have developed fault simulation techniques [refs.] for circuits described at the:
gate and macro gate level;
switch level;
that provide fault coverage results that are more reliable than those achievable by functional testing than conventional techniques.

As regards static current (Iddq) techniques, fault simulation and test generation algorithms taking into account the accuracy of the current sensor have been developed.


Microelectronics page CAD page

DEIS - University of Bologna, Italy / mfavalli@deis.unibo.it