Design For Testability

Problems regarding Built-In Self-Test circuits have been studied with regard to:
the problem of evaluating the aliasing probability in Signature Analysis for which an analytical expression have been found [refs.];
the development of testability measures to be used in pseudorandom testing to estimate fault coverage values [refs.].
Techniques of Design For Testability for CMOS circuits have been developed to make them testable with respect to bridging and delay faults that are difficult to be detected with conventional techniques [refs.].

The design of CMOS self-checking circuits has been addressed by finding [refs.]:

rules for the design of functional units and checkers testable with respect to resistive bridging faults;
novel CMOS checkers for 1/n , m/n and Berger codes;
a checker for delay faults that differently from conventional techniques is capable to account for dynamic failures.
Techniques for the analysis of the reliability and the design of Fault Tolerant combinational circuits have been developed based on a new boolean representation of the network and of faults.


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DEIS - University of Bologna, Italy / mfavalli@deis.unibo.it