n. 1
Algorithms for power consumption reduction and speed enhancement in
high performance parallel multipliers
Rafael Fried
PA PA A    ACCEPTED


n. 2
Cosimulation for ultra low power systems
J.P. Meunier, Steven Chau and Marty Rana
PA PA R    ACCEPTED

n. 3
High level analog/digital partitioning in low power signal
processing applications
S. Donnay, G. Gielen and W. Sansen
A A PA    ACCEPTED

n. 4
Delay propagation term for submicron interconnect
E. Vanier and D. Deschacht
PR A    ACCEPTED
n. 5
Switch-level timing with power evaluation
I. Egorov and A. Zinoviev
PR R R    ACCEPTED

n. 6
Carry circuit depth optimization by BDD based decomposition
A. Kornilov, T. Isaeva and V. Syngaevsky
PR PA PR    ACCEPTED

n. 7
Extended 1/f MOSFET model for circuit simulation. Application to
SOI MOS Devices
B. Iniguez, M. Tambani, V. Dessard and D. Flandre
R PA PR    ACCEPTED
s
n. 8
Switch-level synthesis and modeling
J. Riera, J. Velasco, L. Ribas and J. Carrabina
PA PA PR    ACCEPTED

n. 9
Leakage power reduction for reactive computation
M. Favalli and C. Metra
A R A    ACCEPTED

n. 10
Performance/Power trade-off in ASIC multiplier
B. Laurent and G. Saucier
A PA PA    ACCEPTED

n. 11
Glitch current peak estimation in CMOS gates
G. Zuo and N. Rumin
A A    ACCEPTED

n. 12
A physically based I-V model of partially depleted SOI MOSFET's
dedicated to deep sub-micron VLSI/CMOS technologies
P. Flatresse, O. Faynot and J.L. Pelloie
PA A    ACCEPTED

n. 13
Delay degradation effect in submicronic CMOS inverters
J. Juan-Chico, M.J. Bellido, A.J. Acosta, A. Barriga and M. Valencia
PA A PA    ACCEPTED
s
n. 14
CONNAN: A computer-Aided Design Tool based on Sharing Information
for Analog Circuit Sizing
D. Marin, J. Escudero and D. Flandre
A A PA   ACCEPTED

n. 15
MOMO: scheduling method for large flow graph
J. Noel, C. Trullemans
A PA A    ACCEPTED

n. 16
A rapid boolean technology mapping applicable to power minimization
R. Ferreira, A-M. Trullemans-Anckaert and R. Jacobi
A A PA    ACCEPTED

n. 17
High level power estimation
R. Peset Llopis
A A PA    ACCEPTED

n. 18
A new CMOS ternary logic design for low-power low-voltage circuits
R. Mariani, R. Pessolano and R. Saletti
A PA PA    ACCEPTED

n. 19
An innovative multiple-valued asynchronous system design technique
F. Pessolano, R. Mariani and R. Saletti
A PA PA    ACCEPTED

n. 20
Energy complexity &
J. Smit
PA PR PR    ACCEPTED

n. 21
Area reduction in asynchronous circuits by signal transition
graph transformations
G.S. Panagiotaras, O.G. Koufopavlou
A PR    ACCEPTED

n. 22
A new method for switching activity estimation of logic
level networks
S. Theodaris, G. Theodoridis
R/PR PA    ACCEPTED

n. 23
A wire capacitance estimation techniques for power consuming
interconnections at high level of abstraction
A. Alvandpour and C. Svensson
PA    ACCEPTED

n. 24
A method to extend the validity of quasi-static SOI MOSFET models
L.F. Ferreira, D. Flandre and P. Jespers
PR PA PA    ACCEPTED
s
n. 25
Signal transition modeling in submicronic CMOS structures
J-M. Daga and D. Auvergne
A PA PR/R    ACCEPTED
modeling
n. 26
Mixed Direct Search and Monte-Carlo techniques produce fast and
robust IC parametric yield estimates
J. Horan and C. Lyden
A PA PA    ACCEPTED
yield
n. 27
Sensitivity of the worst case dynamic power estimation on delay
and filtering models
S. Manich and J. Figueras
A A PA    ACCEPTED

n. 28
On estimating leakage power consumption for submicron CMOS digital
circuits
A. Ferre' and J. Figueras
PA PA PA    ACCEPTED

n. 29
Comparison of the BSIM3 and EKV model parameter extraction
methodologies with a direct search optimization method
J.L. Gomez-Cipriano and S. Bampi
PR PR PR    ACCEPTED

n. 30
Probability based delay analysis and tuning of VLSI circuits using
a variance-covariance method
I.J. Osele and R. Sridhar
PR A    ACCEPTED
timing
n. 31
Area/Time/Power space exploration in module selection for DSP
high level synthesis
S. Gailhard, O. Sentieys, N. Julien and E. Martin
PA PR    ACCEPTED

n. 32
Simulation and optimization aid for analog circuits
M. Wolf, F. Schafer and U. Kleine
R PA    ACCEPTED

n. 33
Design problems of low-voltage operational amplifiers in the
CMOS technology
Z. Ciota, M. Napieralska and A. Napieralski
R PR    ACCEPTED

n. 34
Estimation of short-circuit power dissipation for static CMOS gates
driving CRC pi load
A. Hirata, H. Onodera and K. Tamaru
A PA    ACCEPTED

n. 35
A strategy for low power FSM design by reducing switching activity
M. Koegst, G. Franke, S. Rulke and K. Feske
A A PA    ACCEPTED

n. 36
S.J. Abou-Samra and A. Guyot
Analytical modelling of spurious transitions in adder circuits
A PA PA   ACCEPTED

n. 37
Accuracy of toggle analysis power estimation
G. Jochens, L. Kruse and W. Nebel
A PA PR    ACCEPTED

n. 38
Sensitivity analysis for the estimation of propagation delay time
in HFET's DCFL circuits
J. Garcia, A. Hernandez, B. Gonzalez, J. del Pino and A. Nunez
R PA R    ACCEPTED

n. 39
Performance analysis and propagation delay time estimation of logic
families with HBTs
J. del Pino, A. Hernandez, J. Garcia, B. Gonzalez and A. Nunez
R PR PA    ACCEPTED

n. 40
If-diagrams: theory and application
A. Prihozhy
A PA    ACCEPTED

n. 41
Power optimization in digital to analog sigma-delta converters
A. Calomarde and A. Rubio
PR PR    ACCEPTED

n. 42
Substrate coupling trends in future CMOS technologies
X. Aragones, J.L. Gonzalez and A. Rubio
A PA    ACCEPTED

n. 43
Instruction Leel Power Optimization
V.A. Koval, N.O. Shpak and S.Y. Yurish
R R R    ACCEPTED