The research interests of Michele Favalli are in the area of digital ICs design, simulation and testing and include:
  • Fault Simulation and Modeling
  • Fault simulation and modeling of unconventional faults in CMOS circuits
  • Gate and macro-gate fault simulation techniques
  • Switch-Level fault simulation techniques
  • Modeling and simulation of break faults
  • Resistive bridging faults in BiCMOS circuits
  • Fault simulation algorithms
  • Fault simulation and test generation algorithms for current testing in CMOS circuits
  • Design for Testability
  • Built-In Self-Test and Pseudorandom Testing
  • Signature analysis
  • Weighted pseudorandom test generation
  • Testability measures
  • Design for testability for CMOS circuits
  • Self-checking circuits
  • Design rules for checkers and functional units
  • CMOS checkers
  • Checkers for functional units
  • Simulation oriented to low-power design of digital ICs
  • Switch-level algorithms for power estimate
  • Glitch power dissipation in CMOS ICs
  • List of pubblications

    Call for papers

    DEIS - University of Bologna, Italy /