Digital ICs simulation

The problem of estimating the power dissipated by digital ICs has been addressed in order to match the growing demand for design techniques supporting low-power applications. In particular, we have:
analyzed the problem of glitch power dissipation in CMOS ICs showing that the glitch power cannot be neglected and that logic level simulation techniques cannot provide accurate estimates of the glitch power [refs.];
developed accurate power estimation techniques at the switch and at the gate level that are based on a simplified transistor model and on electrical level characterization procedures, respectively.


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DEIS - University of Bologna, Italy / mfavalli@deis.unibo.it