All Micrel group Publications

337 publications



  1. G. Wexler,   B. Riccò
    The effects of anisotropy on a hydrogenic Hamiltonian in an electric field
    The Philosophical Magazine
    vol 31, p. 609, 1975.


    (Ref: 219)

  2. J. Bordas,   B. Riccò
    Electric field effects on anisotropic excitons in lead iodide
    Physica Status Solidi (b)
    vol 67, p. 577, 1975.


    (Ref: 220)

  3. B. Riccò
    Density of states of layer compounds: 2H-NbSe2
    Physica Status Solidi (b)
    vol. 77, p. 287, 1976.


    (Ref: 221)

  4. G. Wexler,   A. Wolley,   B. Riccò
    Does one need the third dimension (normal to the layers) in band-structure for layer compounds?
    Solid-State Physics Conference
    Manchester (U.K.), 1976.


    (Ref: 258)

  5. B. Riccò
    Fermi surface and charge density waves in niobium diselenide
    Solid-State Communications
    vol. 22, p. 331, 1977.


    (Ref: 222)

  6. O. Andrisano,   L. Calandrino,   B. Riccò
    On the performance of CCD channel filters for telephone systems
    Alta Frequenza - Rivista di Elettronica
    vol. XLVI, p. 374, 1977.


    (Ref: 292)

  7. F. Molo,   B. Riccò
    Application of CCDs to FDM channel filtering: a phase-cancellation system
    IEE Electronics Letters
    vol. 13, p. 704, 1977.


    (Ref: 225)

  8. N. J. Doran,   G. Wexler,   V. Heine,   B. Riccò
    The origin of charge density waves in the 2H-polytypes of the group-V layer compounds
    Il Nuovo Cimento
    vol. 38B, p. 544, 1977.


    (Ref: 224)

  9. M. Finetti,   A. M. Mazzone,   L. Passari,   B. Riccò,   E. Susi
    Temperature dependent conductivity of closely compensated phosphorous-doped silicon
    The Philosophical Magazine
    vol. 35, p. 1141, 1977.


    (Ref: 223)

  10. N. J. Doran,   B. Riccò,   D. J. Titterington,   G. Wexler
    A tight-binding fit to the band-structure of 2H-NbSe2 and NbS2
    The Journal of Physics C
    vol. 11, p. 685, 1978.


    (Ref: 226)

  11. B. Riccò,   H. Wallinga
    Analysis of tap weight errors in CCD transversal filters
    European Solid-State Circuits Conference (ESSCIRC)
    p. 89, 1978.


    (Ref: 259)

  12. G. Baccarani,   M. Impronta,   B. Riccò,   P. Ferla
    I-V characteristics of polycrystalline silicon resistors
    Revue de Physique Appliquee
    vol. 13, p. 777, 1978.


    (Ref: 229)

  13. G. Baccarani,   B. Riccò,   G. Spadini
    Transport properties of polycrystalline silicon films
    Journal of Applied Physics
    vol 49, p. 5565, 1978.


    (Ref: 228)

  14. N. J. Doran,   B. Riccò,   M. Schreiber,   D. J. Titterington,   G. Wexler
    The electronic susceptibility and charge density waves in 2H-layer compounds
    The Journal of Physics C
    vol. 11, p. 699, 1978.


    (Ref: 227)

  15. J. W. Pathuis,   H. Wallinga,   B. Riccò
    A CCD phase-cancellation system for single-sideband modulation
    International Conference on Charge Coupled Devices
    p. 205, 1979.


    (Ref: 260)

  16. G. Baccarani,   F. Landini,   B. Riccò
    A depletion-mode MOSFET model including a field-dependent surface mobility
    Proceedings of the IEE
    vol. 127, p. 62, 1980.


    (Ref: 230)

  17. F. Fantini,   B. Riccò
    Ultimate limits of MOS device dimensions and their effects on reliability
    International Conference on Reliability and Maintenability
    Perros-Guirec, p. 499, 1980.


    (Ref: 261)

  18. G. B. Gallimberti,   R. Poluzzi,   G. Baccarani,   B. Riccò
    A single-channel PCM voice CODEC in nMOS technology
    Alta Frequenza - Rivista di Elettronica
    vol. L, p. 294, 1981.


    (Ref: 293)

  19. C. Lombardi,   P. Olivo,   B. Riccò,   E. Sangiorgi,   M. Vanzi
    Hot-electrons in MOS transistors: lateral distribution of the trapped oxide charge
    IEEE Electron Device Letters
    vol. EDL-3, p. 215, 1982.


    (Ref: 231)

  20. P. Olivo,   B. Riccò,   E. Sangiorgi
    Charge trapped within thin SiO2 films in the tunneling regime
    European Solid State Device Research Conference (ESSDERC)
    p. 195, 1982.


    (Ref: 262)

  21. P. Olivo,   B. Riccò,   E. Sangiorgi
    Electron trapping/detrapping within thin SiO2 in the high-field tunneling regime
    Journal of Applied Physics
    vol 54, p. 5267, 1983.


    (Ref: 232)

  22. B. Riccò,   M. Ya. Azbel,   M. H. Brodsky
    A novel mechanism for tunneling and breakdown in thin SiO2 films
    Phys. Rev. Lett.
    vol 51, p. 1795, 1983.


    (Ref: 234)

  23. C. Lombardi,   P. Olivo,   B. Riccò,   E. Sangiorgi,   M. Vanzi
    Two-dimensional effects in hot-electron modified MOSFETs
    IEEE Transactions on Electron Devices
    vol. ED-30, p. 1416, 1983.


    (Ref: 233)

  24. B. Riccò,   M. Ya. Azbel
    The physics of resonant tunneling: the 1D double barrier case
    Phys. Rev. B
    vol. 29, p. 1970, 1984.


    (Ref: 235)

  25. A. Modelli,   B. Riccò
    Electric field and current dependence of SiO2 intrinsic breakdown
    IEEE International Electron Device Meeting (IEDM)
    p. 148, 1984.


    (Ref: 256)

  26. B. Riccò,   E. Sangiorgi,   D. Cantarelli
    Low-voltage hot-electron effects in short-channel MOSFETs
    IEEE International Electron Device Meeting (IEDM)
    p. 92, 1984.


    (Ref: 255)

  27. B. Riccò
    Effects of channel geometry on FETs' output conductance in saturation
    IEEE Electron Device Letters
    vol. EDL-5, p. 353, 1984.


    (Ref: 240)

  28. B. Riccò,   J. M. C. Stork,   M. Arienzo
    Characterization of non-ohmic behavior of emitter contacts of bipolar transistors
    IEEE Electron Device Letters
    vol. ED-5, p. 221, 1984.


    (Ref: 239)

  29. B. Riccò,   M. V. Fischetti
    Temperature dependence of the current in SiO2 in the high field tunneling regime
    Journal of Applied Physics
    vol. 55, p. 221, 1984.


    (Ref: 238)

  30. B. Riccò,   M. Ya. Azbel
    Tunneling through a multiwell one-dimensional structure
    Phys. Rev. B
    vol. 29, p. 4356, 1984.


    (Ref: 237)

  31. Z. Yu,   B. Riccò,   R. W. Dutton
    A comprehensive analitycal and numerical model of polysilicon emitter contacts in bipolar transistors
    IEEE Transactions on Electron Devices
    vol. ED-31, p. 773, 1984.


    (Ref: 236)

  32. M. V. Fischetti,   B. Riccò
    Hot-electron-induced defects at the Si-SiO2 interface at high fields at 295 and 77 K
    Journal of Applied Physics
    vol. 57, p. 2854, 1985.


    (Ref: 241)

  33. P. Olivo,   B. Riccò,   B. Neri
    Noise characteristics of the current tunneling through thin SiO2 films at the onset of dielectric breakdown
    European Solid State Device Research Conference (ESSDERC)
    p. 102, 1985.


    (Ref: 263)

  34. E. Sangiorgi,   B. Riccò,   P. Olivo
    Hot-electrons and holes in MOSFETs biased below the Si-SiO2 interfacial barrier
    IEEE Electron Device Letters
    vol. EDL-6, p. 513, 1985.


    (Ref: 245)

  35. W.I. Wang,   E. E. Mendez,   B. Riccò,   L. Esaki
    Resonant tunneling of holes in quantum-well heterostructures
    Journal of Vacuum Science Technology
    vol. B 3, p. 1149, 1985.


    (Ref: 244)

  36. A. D'Amico,   G. Fortunato,   W. Ruihua,   B. Riccò,   P. Olivo
    Transient current response in Pd-SiO2-Si structures during hydrogen absorption and desorption
    Journal of Applied Physics
    vol. 58, p. 3931, 1985.


    (Ref: 243)

  37. E. E. Mendez,   W. I. Wang,   B. Riccò,   L. Esaki
    Resonant tunneling of holes in AlAs-GaAs-AlAs heterostructures
    Applied Physics Letters
    vol. 47, p. 415, 1985.


    (Ref: 242)

  38. B. Riccò,   P. Olivo
    Space-charge limitations of tunneling resonances
    Superlattices and Microstructures
    vol. 2, p. 79, 1986.


    (Ref: 246)

  39. B. Riccò
    High-speed digital ICs: a comparison between silicon and GaAs
    Alta Frequenza - Rivista di Elettronica
    vol. LV, p. 215, 1986.


    (Ref: 294)

  40. E. Sangiorgi,   B. Riccò,   F. Venturi
    An efficient Monte-Carlo simulator for MOS devices
    International Workshop on Numerical Modeling (NUPAD I)
    Santa Clara (California), 1986.


    (Ref: 264)

  41. B. Riccò,   E. Sangiorgi,   F. Venturi,   P. Lugli
    Monte-Carlo modeling of hot electron gate current in MOSFETs
    IEEE International Electron Device Meeting (IEDM)
    p. 559, 1986.


    (Ref: 257)

  42. P. Olivo,   B. Riccò,   E. Sangiorgi
    High-field-induced voltage-dependent oxide charge
    Applied Physics Letters
    vol. 48, p. 1135, 1986.


    (Ref: 247)

  43. E. Sangiorgi,   B. Riccò,   L. Selmi
    Three-dimensional distribution of CMOS latch-up current
    IEEE Electron Device Letters
    vol. EDL 8, p. 154, 1987.


    (Ref: 248)

  44. L. Selmi,   F. Venturi,   E. Sangiorgi,   B. Riccò
    Three-dimensional distribution of latch-up current in scaled CMOS structures
    European Solid State Device Research Conference (ESSDERC)
    p. 783, 1987.


    (Ref: 269)

  45. C. Mantilli,   F. Venturi,   B. Riccò,   E. Sangiorgi
    A Monte-Carlo approach to the study of the drift-diffusion transport model
    European Solid State Device Research Conference (ESSDERC)
    p. 173, 1987.


    (Ref: 268)

  46. E. Sangiorgi,   F. Venturi,   B. Riccò
    Monte-Carlo analysis of VLSI devices
    International Conference on Industrial and Applied Mathematics (ICIAM 87)
    Paris, 1987.


    (Ref: 267)

  47. B. Riccò,   P. Olivo,   T. N. Nguyen
    Quantum mechanical effects on MOS capacitance
    INFOS
    , 1987.


    (Ref: 266)

  48. T. N. Nguyen,   P. Olivo,   B. Riccò
    A new failure mode of very thin thermal SiO2 films
    Inter. Rel. Phys. Symp.
    p. 66, 1987.


    (Ref: 265)

  49. P. Olivo,   B. Riccò,   T. N. Kuan,   S. J. Jeng
    Evidence of the role of defects near the injecting interface in determining SiO2 breakdown
    Applied Physics Letters
    vol. 51, p. 2245, 1987.


    (Ref: 251)

  50. B. Neri,   P. Olivo,   B. Riccò
    Low-frequency noise in silicon-gate MOS capacitors before oxide breakdown
    Applied Physics Letters
    vol. 51, p. 2167, 1987.


    (Ref: 250)

  51. B. Riccò,   E. Sangiorgi,   G. Ferriani
    High-holding voltage CMOS technology with lightly doped source and drain regions
    IEEE Transactions on Electron Devices
    vol. ED 34, p. 810, 1987.


    (Ref: 249)

  52. E. Sangiorgi,   M. R. Pinto,   F. Venturi,   W. Fichtner
    A Hot-Carrier Analysis of Submicrometer MOSFET's
    IEEE Electron Device Letters
    vol. EDL-9, pp. 13-16, Jan., 1988.


    (Ref: 0)

  53. B. Riccò,   L. Selmi,   E. Sangiorgi
    A Novel Method to Determine the Source and Drain Resistances of Individual MOSFETs
    IEEE International Electron Device Meeting (IEDM)
    pp. 122-125, S. Francisco (CA.), Dec., 1988.


    (Ref: 11)

  54. P. Olivo,   T. N. Nguyen,   B. Riccò
    High-Field-Induced Degradation in Ultra Thin SiO2 Films
    IEEE Transactions on Electron Devices
    vol. ED-35, pp. 2259-2267, Dec., 1988.


    (Ref: 10)

  55. R. Menozzi,   L. Selmi,   E. Sangiorgi,   G. Crisenza,   T. Cavioni,   B. Riccò
    Layout Dependence of CMOS Latch-up
    IEEE Transactions on Electron Devices
    vol. ED-35, pp. 1892-1901, Nov., 1988.


    (Ref: 9)

  56. T. N. Nguyen,   P. Olivo,   B. Riccò
    Reliability Issues for Ultra-Thin Insulators
    Electrochemical Society Symposium on Reliability of Semiconductor Devices and Interconnections
    Chicago (Ill), Oct., 1988.


    (Ref: 8)

  57. M. Damiani,   P. Olivo,   M. Favalli,   B. Riccò
    Aliasing Errors in Signature Analysis Testing of Integrated Circuits
    IEEE International Conference on Computer Design (ICCD)
    pp. 458-461, Rye Brook (N.Y), Oct. , 1988.


    (Ref: 7)

  58. F. Venturi,   R. K. Smith,   E. Sangiorgi,   M. R. Pinto,   B. Riccò
    A New Coupling Scheme for a Self-Consistent Poisson and Monte Carlo Device Simulator
    International Conference on Simulation of Semiconductor Devices and Processes (SISDEP-88)
    pp. 383-386, Sep., 1988.


    (Ref: 6)

  59. M. Lanzoni,   C. Morandi,   B. Riccò
    Macchine Automatiche per il Collaudo dei Circuiti Integrati Digitali
    Alta Frequenza - Rivista di Elettronica
    vol. LVII, pp. 105-115, May., 1988.


    (Ref: 5)

  60. L. Selmi,   E. Sangiorgi,   G. Crisenza,   D. Re,   B. Riccò
    Hysteresis Cycle in the Latch-up Characteristics of Wide CMOS Structures
    IEEE Electron Devices Letters
    vol. EDL-9, pp. 214-217, May., 1988.


    (Ref: 4)

  61. B. Riccò,   P. Olivo,   T. N. Nguyen,   T. S. Kuan,   G. Ferriani
    Oxide Thickness Determination in Thin Insulator MOS Structure
    IEEE Transactions on Electron Devices
    vol. 35, pp. 432-438, Apr., 1988.


    (Ref: 3)

  62. F. Venturi,   R. K. Smith,   E. Sangiorgi,   M. R. Pinto,   B. Riccò
    A Self-Consistent Monte Carlo Simulator for Deep Submicrom MOSFET's
    International Workshop on Numerical Modeling (NUPAD II)
    San Diego (California), May., 1988.


    (Ref: 2)

  63. E. Sangiorgi,   F. Venturi,   B. Riccò
    MOS2, an Efficient MonteCarlo simulator for MOS devices
    IEEE Transactions on Computer Aided Design
    vol. CAD-7, pp. 259-271, Feb., 1988.


    (Ref: 1)

  64. F. Venturi,   R.K. Smith,   E. Sangiorgi,   M.R. Pinto,   B. Riccò
    A General Purpose Device Simulator Coupling Poisson and Monte Carlo Transport with Applications to Deep Submicron MOSFET's
    IEEE Transactions on Computer Aided Design
    vol. CAD-8, pp. 360-369, Apr., 1989.


    (Ref: 12)

  65. B. Riccò
    Circuiti digitali bipolari per alte velocità
    Alta Frequenza - Rivista di Elettronica
    vol. 10, pp. 215-227, Oct., 1989.


    (Ref: 30)

  66. F. Venturi,   E. Sangiorgi,   R. Brunetti,   C. Jacoboni,   B. Riccò
    Monte Carlo Simulation of Electron Heating in Scaled Deep Sub-micron MOSFETs
    IEEE International Electron Device Meeting (IEDM)
    pp. 485-488, Washington, Dec., 1989.


    (Ref: 29)

  67. B. Neri,   R. Saletti,   P. Olivo
    Current Noise Spectra and Fluctuations Before Breakdown in Thin Silicon Oxides
    ESPRIT Workshop on the Characterization and Growth of Thin Dielectrics in Microelectronics
    Cork (Ireland), Oct., 1989.


    (Ref: 28)

  68. S. Ercolani,   M. Favalli,   M. Damiani,   P. Olivo,   B. Riccò
    Improved Testability Evaluations in Combinational Logic Networks
    IEEE International Conference on Computer Design (ICCD)
    pp. 352-355, Cambridge (Mass.), Oct., 1989.


    (Ref: 27)

  69. E. Sangiorgi,   F. Venturi,   B. Riccò
    Parallel and Vector Algorithms for Monte Carlo Simulation of Semiconductor Devices
    International Youth Workshop on Monte Carlo methods and Parallel Algorithms
    Primorsko (Bulgaria), Sep., 1989.


    (Ref: 26)

  70. P. Olivo,   M. Damiani,   B. Riccò
    On the Design of Multiple-Input Shift-Registers for Signature Analysis Testing
    IEEE International Test Conference (ITC)
    p. 936, Washington (USA), Aug., 1989.


    (Ref: 25)

  71. B. Neri,   A. Marini,   R. Saletti,   P. Olivo
    Current Noise Spectra and Fluctuations Before Breakdown in Thin Silicon Oxides Noise in Physical Systems
    International Conference on Noise in Physical Systems, ed. by A. Ambrózy (Akademiai Kiado, Budapest, 1990),
    pp. 267-270, Budapest (Hungary), Aug., 1989.


    (Ref: 24)

  72. M. Lanzoni,   P. Olivo,   B. Riccò
    A Testing Technique to Characterize E2PROM Aging and Endurance
    IEEE International Test Conference (ITC)
    pp. 391-396, Washington (USA), Aug., 1989.


    (Ref: 23)

  73. M. Favalli,   P. Olivo,   M. Damiani,   B. Riccò
    CMOS Design for Improved IC Testability
    IEEE International Test Conference (ITC)
    p. 934, Washington (USA), Aug., 1989.


    (Ref: 22)

  74. R. Brunetti,   C. Jacoboni,   F. Venturi,   E. Sangiorgi,   B. Riccò
    A Many-Band Silicon Model for Hot-Electron Transport at High Energies
    International Conference on Hot Carriers in Semiconductors
    Scottsdale, Arizona, Jul., 1989.


    (Ref: 21)

  75. S. Ercolani,   M. Favalli,   M. Damiani,   P. Olivo,   B. Riccò
    Estimate of Signal Probability in Combinational Logic Network
    IEEE European Test Conference (ETC)
    pp. 132-138, Paris (France), Apr., 1989.


    (Ref: 19)

  76. M. Damiani,   P. Olivo,   M. Favalli,   S. Ercolani,   B. Riccò
    Aliasing in Signature Analysis Testing with Multiple-Input Shift-Registers
    IEEE European Test Conference (ETC)
    pp. 346-353, Paris (France), Apr., 1989.


    (Ref: 18)

  77. R. Brunetti,   C. Jacoboni,   F. Venturi,   E. Sangiorgi,   B. Riccò
    A Many-Band Silicon Model for Hot-Electron Transport at High Energies
    Solid State Electronics
    vol. 32, pp. 1663-1667, Dec., 1989.


    (Ref: 17)

  78. M. Damiani,   P. Olivo,   M. Favalli,   B. Riccò
    An Analytical Model for the Aliasing Probability in Signature Analysis Testing
    IEEE Transactions on Computer Aided Design
    vol. CAD-8, pp. 1133-1144, Nov., 1989.


    (Ref: 16)

  79. C. Fiegna,   L. Selmi,   E. Sangiorgi,   B. Riccò
    Three Dimensional Effects in Dynamically Triggered CMOS Latch-up
    IEEE Transactions on Electron Devices
    vol. ED-36, pp. 1683-1690, Sep., 1989.


    (Ref: 15)

  80. L. Selmi,   E. Sangiorgi,   B. Riccò
    Parameter Extraction from I-V Characteristics of Single MOSFETs
    IEEE Transactions on Electron Devices
    vol. ED-36, pp. 1094-1101, Jun., 1989.


    (Ref: 14)

  81. M. Lanzoni,   M. Manfredi,   L. Selmi,   E. Sangiorgi,   B. Riccò
    Hot-Electron-Induced Photon Energies in n-channel MOSFETs Operating at 77 and 300°K
    IEEE Electron Device Letters
    vol. EDL-10, pp. 173-176, May., 1989.


    (Ref: 13)

  82. B. Riccò,   F. Fantini,   F. Magistrali,   P. Brambilla
    Reliability of GaAs MESFETs
    Nato Advanced Research Workshop on Semiconductor Device Reliability, Heraklio (Greece), June 1989, in Semiconductor Device Reliability,
    edited by A. Christou and B. A Unger, (Kluwer Academic Publ., Dordrecht NL) pp. 455-469, 1990.


    (Ref: 20)

  83. D. Cassi,   B. Riccò
    An analytical model of the energy distribution of hot-electrons
    IEEE Transactions on Electron Devices
    vol. ED 37, p. 1514, 1990.


    (Ref: 252)

  84. S. Sugino,   Z. Yu,   F. Venturi,   R. Dutton
    Modeling of Bias-Stress Dependent Transconductance Degradation of Submicron MOSFETs
    IEEE International Electron Device Meeting (IEDM)
    S. Francisco (California), pp. 459-462, Dec., 1990.


    (Ref: 55)

  85. F. Venturi,   C. Fiegna,   A. Abramo,   E. Sangiorgi,   B. Riccò
    Hot-Holes Generation and Transport in n-MOSFETs: a Monte Carlo Investigation
    IEEE International Electron Device Meeting (IEDM)
    S. Francisco (California), pp. 455-458, Dec., 1990.


    (Ref: 54)

  86. M. Lanzoni,   E. Sangiorgi,   C. Fiegna,   M. Manfredi,   B. Riccò
    Extended (1.1-2.9 eV) Hot-Carrier Induced Photon Emission in n-Channel MOSFETs
    IEEE International Electron Device Meeting (IEDM)
    S. Francisco (California), pp. 69-72, Dec., 1990.


    (Ref: 53)

  87. C. Fiegna,   F. Venturi,   E. Sangiorgi,   B. Riccò
    Efficient Non-Local Modeling of Electron Energy Distribution in Sub-micron MOSFETs
    IEEE International Electron Device Meeting (IEDM)
    S. Francisco (California), pp. 451-454, Dec., 1990.


    (Ref: 52)

  88. J. Suñé,   P. Olivo,   B. Riccò
    Quantum Effects in the Accumulation Layers of MOS Structures at Room Temperature
    IEEE Semiconductor Interface Specialist Conference (SISC)
    San Diego (California), paper P1.3, Dec., 1990.


    (Ref: 51)

  89. L. Selmi,   D. B. Estreich
    An accurate System for automated On-wafer Characterization of Three-port Devices
    IEEE GaAs IC Symposium
    New Orleans, pp. 343-346, Oct., 1990.


    (Ref: 50)

  90. J. Suñé,   P. Olivo,   B. Riccò
    Quantum Effects in the Accumulation Layers of MOS Structures at Room Temperature
    European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF) (ESPRIT Workshop on the Characterization and Growth of Thin Dielectrics in Microelectronics)
    Bari (Italy), pp. 515-518, Oct., 1990.


    (Ref: 49)

  91. R. Menozzi,   L. Selmi,   E. Sangiorgi,   B. Riccò
    Effects of the Interaction of Neighboring Structures on the Latch-up Behavior of CMOS ICs
    European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF)
    Bari (Italy), pp. 175-182, Oct., 1990.


    (Ref: 48)

  92. M. Lanzoni,   R. Menozzi,   C. Riva,   P. Olivo,   B. Riccò
    Evaluation of E2PROM Data Retention by Field Acceleration
    European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF)
    Bari (Italy), pp. 329-334, Oct., 1990.


    (Ref: 47)

  93. R. Menozzi,   M. Lanzoni,   L. Selmi,   B. Riccò
    An Improved Procedure to Test CMOS ICs for Latch-up
    IEEE International Test Conference (ITC)
    Washinghton D.C., pp 1028-1084, Sep., 1990.


    (Ref: 46)

  94. C. Fiegna,   F. Venturi,   M. Melanotte,   E. Sangiorgi,   B. Riccò
    Simulation of EPROM Writing
    European Solid State Device Research Conference (ESSDERC)
    Nottingham (U.K.), Sep., 1990.


    (Ref: 45)

  95. B. Riccò,   E. Sangiorgi,   F. Venturi
    Montecarlo Simulation for Electron Devices
    VLSI Process/Device modeling Workshop
    Kawasaki (Japan), pp. 6-9, Aug., 1990.


    (Ref: 44)

  96. F. Venturi,   E. Sangiorgi,   R. Brunetti,   W. Quade,   C. Jacoboni,   B. Riccò
    An Efficient Monte Carlo Simulator for High-Energy Electrons and Holes in MOSFET's
    Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits (NUPAD III)
    Honolulu (Hawaii), pp. 43-44, Jun., 1990.


    (Ref: 43)

  97. P. Olivo,   M. Damiani
    An Analytical Criterion for the Choice of Optimal Registers for Signature Analysis Testing
    IEEE European Workshop on Design for Testability
    Segovia (Spain), Jun., 1990.


    (Ref: 42)

  98. M. Favalli,   P. Olivo,   B. Riccò
    A Circuit for the Detection of Delay Faults in CMOS ICs
    IEEE European Workshop on Design for Testability
    Segovia (Spain), Jun., 1990.


    (Ref: 41)

  99. M. R. Pinto,   W. M. Coughram,   C. S. Rafferty,   R. K. Smith,   E. Sangiorgi
    Device Simulation for Silicon ULSI
    International Workshop on Computational Electronics
    Computational Electronics: Semiconductor Transport and Device Simulation, edited by K. Hess, J. P. Leburton, U. Ravaioli (Kluwer Academic Publishers, 1991), pp. 3-13, Urbana-Champagne (Illinois), May., 1990.


    (Ref: 40)

  100. M. Damiani,   P. Olivo,   B. Riccò
    Choice of the Optimal Primitive Polynomial for Signature Analysis Testing
    IEEE Design For Testability Workshop
    Vail (Colorado), Apr., 1990.


    (Ref: 39)

  101. M. Damiani,   P. Olivo
    Aliasing in Parallel-Input Linear Signature Analysis Testing
    IEEE Built-in Self-Test (BIST) Workshop
    Charleston (S. Carolina), Mar., 1990.


    (Ref: 38)

  102. M. Favalli,   P. Olivo,   B. Riccò
    Progettazione Orientata al Collaudo di Circuiti Integrati Digitali
    Alta Frequenza - Rivista di Elettronica
    vol. II, pp. 55-64, Apr., 1990.


    (Ref: 37)

  103. M. Damiani,   P. Olivo,   M. Favalli,   S. Ercolani,   B. Riccò
    Aliasing in Signature Analysis Testing with Multiple-Input Shift-Registers
    IEEE Transactions on Computer Aided Design
    vol. CAD-9, pp. 1344-1353, Dec., 1990.


    (Ref: 36)

  104. R. Saletti,   B. Neri,   P. Olivo,   A. Modelli
    Correlated Fluctuations and Noise Spectra of Tunneling and Substrate Currents Before Breakdown in Thin-Oxide MOS Devices
    IEEE Transactions on Electron Devices
    vol. ED-37, pp. 2411-2413, Nov., 1990.


    (Ref: 35)

  105. M. Favalli,   P. Olivo,   M. Damiani,   B. Riccò
    Novel Design for Testability Schemes for CMOS ICs
    IEEE Journal of Solid State Circuits
    vol. SC-25, pp. 1239-1246, Oct., 1990.


    (Ref: 34)

  106. R. Menozzi,   M. Lanzoni,   C. Fiegna,   E. Sangiorgi,   B. Riccò
    Latch-up Testing in CMOS ICs
    IEEE Journal of Solid State Circuits
    vol. SC-25, pp. 1010-1014, Aug., 1990.


    (Ref: 33)

  107. E. Sangiorgi,   C. Fiegna,   R. Menozzi,   L. Selmi,   B. Riccò
    Latch-up in CMOS Circuits: a Review
    European Transactions on Telecommunications and Related Technologies
    vol. 1, pp. 107-119, May., 1990.


    (Ref: 32)

  108. M. Lanzoni,   R. Menozzi,   P. Olivo,   B. Riccò,   A. Haardt
    Testing of E2PROM Aging and Endurance: a Case Study
    European Transactions on Telecommunications and Related Technologies
    vol. 1, pp. 201-208, Mar., 1990.


    (Ref: 31)

  109. P. Olivo,   T. N. Nguyen,   B. Riccò
    Influence of Localized Latent Defects on Electrical Breakdown of Thin Insulators
    IEEE Transactions on Electron Devices
    vol. ED-38, pp. 527-531, Mar., 1991.


    (Ref: 56)

  110. E. Sangiorgi,   F. Venturi,   C. Fiegna,   A. Abramo,   B. Riccò,   F. Capasso
    Non-local effects on the electron energy distribution in short devices under high-field conditions
    Hot carriers in Semicoductors Conference
    Nara (Japan), Jul., 1991.


    (Ref: 270)

  111. J. Suñé,   P. Olivo,     M. Lanzoni,   B. Riccò
    Non Steady-State Simulation and Characterization of Fowler-Nordheim Tunneling in Floating Gate EEPROMs
    IEEE Semiconductor Interface Specialist Conference (SISC)
    Orlando (Fl), paper P1.2, Dec., 1991.


    (Ref: 90)

  112. J. Suñé,   M. Lanzoni,   R. Bez,   P. Olivo,   B. Riccò
    Transient Simulation of the Erase Cycle of Floating Gate EEPROMs
    IEEE International Electron Device Meeting (IEDM)
    Washington D.C., pp. 905-908, Dec., 1991.


    (Ref: 89)

  113. C. Fiegna,   E. Sangiorgi,   F. Venturi,   A. Abramo,   B. Riccò
    Modeling of High Energy Electrons in n-MOSFETs
    IEEE International Electron Device Meeting (IEDM)
    Washington D.C., pp. 503-506, Dec., 1991.


    (Ref: 88)

  114. R. Menozzi,   L. Selmi,   P. Gandolfi,   B. Riccò
    Extraction of the Series Resistances and Effective Channel Length of GaAs MESFETs by means of Electrical Methods: A Numerical Analysis
    IEEE International Electron Device Meeting (IEDM)
    Washington D.C., pp. 341-344, Dec., 1991.


    (Ref: 87)

  115. L. Selmi,   B. Riccò
    Thermal Characterization of GaAs MESFETs by means of Pulsed Measurements
    IEEE International Electron Device Meeting (IEDM)
    Washington D.C., pp. 255-258, Dec., 1991.


    (Ref: 86)

  116. F. Venturi,   A. Abramo,   E. Sangiorgi,   J.M. Higman,   C. Fiegna,   B. Riccò
    An Isotropic best-Fitting Band Model for Electron and Hole Transport in Silicon
    IEEE International Electron Device Meeting (IEDM)
    Washington D.C., pp. 119-122, Dec., 1991.


    (Ref: 85)

  117. P. Pavan,   E. Zanoni,   R. Menozzi,   L. Selmi
    Adjacent structure interactions in the Latch-up triggering of CMOS twin-tub and epitaxial technologies
    European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF)
    Bordeaux (France), pp. 333-338, Oct., 1991.


    (Ref: 84)

  118. L. Selmi,   D. B. Estreich,   B. Riccò
    Application of Bridged T-coils to the design of Multiplicative Gain MMIC Amplifiers
    IEEE Solid State Circuits Conference
    Milan (Italy), pp. 173-176, Sep., 1991.


    (Ref: 83)

  119. A. Abramo,   C. Fiegna,   F. Venturi,   R. Brunetti,   E. Sangiorgi,   C. Bergonzoni,   B. Riccò
    A New Microscopic Model for Hole Transport in Silicon with Application to Sub-Micron LDD MOSFET's
    International Conference on Simulation of Semiconductor Devices and Processes (SISDEP)
    Zurich (Switzerland), pp. 257-263, Sep., 1991.


    (Ref: 82)

  120. A. Abramo,   R. Brunetti,   F. Venturi,   E. Sangiorgi,   C. Fiegna,   B. Riccò
    A Multi-Band Model for Hole Transport in Silicon
    Hot carriers in Semicoductors Conference
    Nara (Japan). Jul., 1991.


    (Ref: 81)

  121. M. Lanzoni,   J. Suñé,   C. Riva,   P. Ghezzi,   P. Olivo,   B. Riccò
    Advanced Spice-Like Modeling of E2PROM Cells
    International Workshop on VLSI Process and Device Modeling
    Oiso (Japan), pp. 134-135, May., 1991.


    (Ref: 80)

  122. C. Fiegna,   E. Sangiorgi,   F. Venturi,   A. Abramo,   B. Riccò
    Optimization of physical parameters for high energy transport simulation in Si based on efficient electron energy distribution calculations
    International Workshop on VLSI Process and Device Modeling
    Oiso (Japan), pp. 40-41, May., 1991.


    (Ref: 79)

  123. M. Favalli,   S. Ercolani,   M. Dalpasso,   P. Olivo,   B. Riccò
    Weighted Pseudorandom Generation for Built-In Self-Test
    IEEE COMPEURO
    Bologna (Italy), pp. 572-574, May., 1991.


    (Ref: 78)

  124. M. Ambanelli,   M. Favalli,   M. Dalpasso,   P. Olivo,   B. Riccò
    Fault Simulation of Multiple Faults in PLAs
    IEEE COMPEURO
    Bologna (Italy), pp. 229-232, May., 1991.


    (Ref: 77)

  125. B. Riccò,   M. Favalli,   P. Olivo
    Comprehensive Fault Modeling and Simulation in CMOS ICs
    IEEE COMPEURO
    Bologna (Italy), pp. 778-785, May., 1991.


    (Ref: 76)

  126. M. Dalpasso,   M. Favalli,   P. Olivo,   B. Riccò
    Switch-Level Fault Simulation by Critical Path Tracing
    IEEE European Test Conference (ETC)
    Munich (Germany), pp. 181-190, Apr., 1991.


    (Ref: 75)

  127. M. Favalli,   P. Olivo,   B. Riccò
    A Probabilistic Fault Model for Analog Faults in CMOS Circuits
    European Design Automation Conference (EDAC)
    Amsterdam (The Nederlands), pp. 85-88, Feb., 1991.


    (Ref: 74)

  128. M. Ambanelli,   M. Favalli,   P. Olivo,   B. Riccò
    Detection of PLA Multiple Crosspoint Faults
    European Design Automation Conference (EDAC)
    Amsterdam (The Nederlands), pp. 80-84, Feb., 1991.


    (Ref: 73)

  129. B. Riccò,   M. Favalli,   L. Selmi
    Logiche di Tipo BiCMOS
    Alta Frequenza - Rivista di Elettronica
    vol. III, pp. 25-36, Jan., 1991.


    (Ref: 72)

  130. A. A. Grimberg,   S. Luryi,   N. L. Schryer,   R. K. Smith,   C. Lee,   U. Ravaioli,   E. Sangiorgi
    Adiabatic Approach to the Dynamics of Nonequilibrium Electron Ensembles in Semiconductors
    Phys. Rev. B
    vol. 44, pp. 10536-10545, Nov., 1991.


    (Ref: 71)

  131. P. Olivo,   J. Suñé,   B. Riccò
    On the Determination of the Si-SiO2 Barrier Height from the Fowler-Nordheim Plot
    IEEE Electron Device Letters
    vol. EDL-12, pp. 620-622, Nov., 1991.


    (Ref: 70)

  132. F. Venturi,   E. Sangiorgi,   R. Brunetti,   W. Quade,   C. Jacoboni,   B. Riccò
    Monte Carlo Simulation of High-Energy Electrons and Holes in Si-n-MOSFET's
    IEEE Transactions on Computer Aided Design
    vol. CAD-10, pp. 1276-1286, Oct., 1991.


    (Ref: 69)

  133. M. Damiani,   P. Olivo,   B. Riccò
    Analysis and Design of Linear Finite State Machine for Signature Analysis Testing
    IEEE Transactions on Computers
    vol. C-40, pp. 1034-1045, Sep., 1991.


    (Ref: 68)

  134. M. Lanzoni,   R. Menozzi,   C. Riva,   P. Olivo,   B. Riccò
    Evaluation of E2PROM Data Retention by Field Acceleration
    Quality and Reliability Engineering International
    vol. 7, pp. 293-297, Jul., 1991.


    (Ref: 67)

  135. R. Menozzi,   L. Selmi,   E. Sangiorgi,   B. Riccò
    Effects of the Interactions of Neighboring Structures on the Latch-up Behavior of CMOS IC's
    IEEE Transactions on Electron Devices
    vol. ED-38, pp. 1978-1981, Aug., 1991.


    (Ref: 66)

  136. F. Venturi,   E. Sangiorgi,   B. Riccò
    The Impact of Voltage Scaling on Electron Heating and Device Performance of Submicrometer MOSFET's
    IEEE Transactions on Electron Devices
    vol. ED-38, pp. 1895-1904, Aug., 1991.


    (Ref: 65)

  137. J. Suñé,   P. Olivo,   B. Riccò
    Self-Consistent Solution of Poisson and Schrödinger Equations in Accumulated Semiconductor-Insulator Interfaces
    Journal of Applied Physics
    vol. 70, pp. 337-345, Jul., 1991.


    (Ref: 64)

  138. M. Lanzoni,   E. Sangiorgi,   C. Fiegna,   M. Manfredi,   B. Riccò
    Extended (1.1 - 2.9 eV) Hot-Carrier-Induced Photon Emission in n-Channel Si MOSFETs
    IEEE Electron Device Letters
    vol. EDL-12, pp. 341-343, Jun., 1991.


    (Ref: 63)

  139. P. Olivo,   Z. A. Weinberg,   K. J. Stein,   D. S. Wen
    Charge Trapping and Retention in Ultra Thin Oxide-Nitride-Oxide Structures
    Solid State Electronics
    vol. 34, pp. 609-611, Jun., 1991.


    (Ref: 62)

  140. M. Favalli,   P. Olivo,   F. Somenzi,   B. Riccò
    Fault Simulation for General FCMOS ICs
    Journal of Electronic Testing, Theory and Applications
    vol. 2, pp. 181-190, Jun., 1991.


    (Ref: 61)

  141. M. Favalli,   P. Olivo,   M. Damiani,   B. Riccò
    Fault Simulation of Unconventional Faults in CMOS Circuits
    IEEE Transactions on Computer Aided Design
    vol. CAD-10, pp. 677-682, May., 1991.


    (Ref: 60)

  142. M. Favalli,   P. Olivo,   B. Riccò
    A Novel Critical Path Heuristic for Fast Fault Grading
    IEEE Transactions on Computer Aided Design
    vol. CAD-10, pp. 544-548, Apr., 1991.


    (Ref: 59)

  143. F. Venturi,   E. Sangiorgi,   S. Luryi,   P. Poli,   L. Rota,   C. Jacoboni
    Energy Oscillations in Electron Transport Across a Triangular Barrier
    IEEE Transactions on Electron Devices
    vol. ED-38, pp. 611-618, Mar., 1991.


    (Ref: 58)

  144. C. Fiegna,   F. Venturi,   M. Melanotte,   E. Sangiorgi,   B. Riccò
    Simple and Efficient Modeling of EPROM Writing
    IEEE Transactions on Electron Devices
    vol. ED-38, pp. 603-610, Mar., 1991.


    (Ref: 57)

  145. A. Abramo,   F. Venturi,   E. Sangiorgi,   C. Fiegna,   B. Riccò,   R. Brunetti,   W. Quade,   C. Jacoboni
    A multi-band model for hole transport in silicon at high energies
    Semiconductor Science and Technology
    vol. 7, pp. 597-600, Apr., 1992.


    (Ref: 91)

  146. L. Selmi,   C. Fiegna,   E.Sangiorgi,   R. Bez,   B. Riccò
    Analysis of Uniform Degradation in n-MOSFETs
    IEEE International Electron Device Meeting (IEDM)
    S. Francisco (California), pp. 729-732, Dec., 1992.


    (Ref: 115)

  147. J. Suñé,   M. Nafrià,   X. Aymerich,   M. Lanzoni,   P. Olivo,   B. Riccò
    Modelo Avanzado de Celdas EEPROM para Simulacion Tipo SPICE
    6° Escuela de Microelectronica
    Laredo (Spain), Sep. , 1992.


    (Ref: 114)

  148. M. Favalli,   M. Dalpasso,   P. Olivo,   B. Riccò
    Analysis of Steady State Detection of Resistive Bridging Faults in BiCMOS Digital Circuits
    IEEE International Test Conference (ITC)
    Baltimore (Maryland), pp. 466-475, Sep., 1992.


    (Ref: 113)

  149. M. Dalpasso,   M. Favalli,   P. Olivo,   B. Riccò
    Parametric Bridging Fault Characterization for the Fault Simulation of Library-Based ICs
    IEEE International Test Conference (ITC)
    Baltimore (Maryland), pp. 486-495, Sep., 1992.


    (Ref: 112)

  150. C. Metra,   M. Favalli,   P. Olivo,   B. Riccò
    CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults
    IEEE International Test Conference (ITC)
    Baltimore (Maryland), pp. 948-957, Sep., 1992.


    (Ref: 111)

  151. L. Selmi,   B. Riccò
    Design of an X-band, Transformer Coupled Amplifier with improved Stability and Layout
    URSI International Symposium on Signals, Systems and Electronics
    Paris (France), pp. 768-771, Sep., 1992.


    (Ref: 110)

  152. E. Sangiorgi,   D. Chen,   M.R. Pinto,   R. W. Dutton
    Comparison between hydrodinamic and MonteCarlo models for silicon device simulation
    URSI International Symposium on Signals, Systems and Electronics
    Paris (France), pp. 620-625, Sep., 1992.


    (Ref: 109)

  153. L. Selmi,   M. Lanzoni,   S. Bigliardi,   E. Sangiorgi
    Photon Emission from sub-micron p-channel MOSFETs Biased at High Fields
    European Solid State Device Research Conference (ESSDERC)
    Leuwen (Belgium), pp. 747-750, Sep. , 1992.


    (Ref: 108)

  154. A. Abramo,   F. Venturi,   E. Sangiorgi,   C. Fiegna,   B. Riccò
    Device simulation of small silicon MOSFET's using the MonteCarlo Method
    Workshop on Parallel Algorithms
    Sofia, Aug. , 1992.


    (Ref: 107)

  155. M. Lanzoni,   M. Favalli,   P. Olivo,   B. Riccò
    An Experimental Study of Testing Techniques for Bridging Faults in CMOS ICs
    IEEE European Worskhop on Design for Testability
    Brugge (Belgium), Jun., 1992.


    (Ref: 106)

  156. C. Metra,   M. Favalli,   P. Olivo,   B. Riccò
    CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults
    IEEE European Worskhop on Design for Testability
    Brugge (Belgium), Jun., 1992.


    (Ref: 105)

  157. M. Favalli,   P. Olivo,   B. Riccò
    Dynamic Effects in the Detection of Bridging Faults in CMOS ICs
    IEEE European Worskhop on Design for Testability
    Brugge (Belgium), Jun. , 1992.


    (Ref: 104)

  158. E. Sangiorgi
    Monte Carlo Simulation of Small Silicon Mosfet's
    International Workshop on Computational Electronics
    Urbana-Champaign (Illinois), May., 1992.


    (Ref: 103)

  159. F. Venturi,   E. Sangiorgi,   C. Fiegna,   A. Abramo,   F. Capasso
    Non-local effects on the electron energy distribution in short devices under high-field conditions
    International Workshop on Computational Electronics
    Urbana-Champaign (Illinois), May., 1992.


    (Ref: 102)

  160. D. Chen,   E. Sangiorgi,   M. R. Pinto,   E. C. Kan,   U. Ravaioli,   R. W. Dutton
    Analysis of Spurious Velocity Overshoot in Hydrodynamic Simulations
    NUPAD
    Seattle (Washington), May. , 1992.


    (Ref: 101)

  161. A. Abramo,   F. Venturi,   E. Sangiorgi,   J. M. Higman,   C. Fiegna,   B. Riccò
    A Numerical Method to Compute Isotropic Band Models From Anisotropic
    NUPAD
    Seattle (Washington), May., 1992.


    (Ref: 100)

  162. M. Favalli,   M. Dalpasso
    Simulazione di guasti in circuiti integrati digitali
    Alta Frequenza - Rivista di Elettronica
    vol. IV, pp. 13-22, Gen. , 1992.


    (Ref: 99)

  163. M. Favalli,   P. Olivo,   B. Riccò
    A Probabilistic Fault Model for "Analog" Faults in Digital CMOS Circuits
    IEEE Transactions on Computer Aided Design
    vol. CAD-11, pp. 1459-1462, Nov. , 1992.


    (Ref: 98)

  164. R. Menozzi,   L. Selmi,   P. Gandolfi,   B. Riccò
    Numerical Analysis of the Gate Voltage Dependence of the Series Resistances and Effective Channel Length of in Submicrometer GaAs MESFET's
    IEEE Transactions on Electron Devices
    vol. ED-39, pp. 2015-2020, Sep., 1992.


    (Ref: 97)

  165. M. Favalli,   P. Olivo,   B. Riccò
    Dynamic Effects in the Detection of Bridging Faults in CMOS ICs
    Journal of Electronic Testing, Theory and Applications
    vol. 3, pp. 197-205, Aug. , 1992.


    (Ref: 96)

  166. J. Suñé,   P. Olivo,   B. Riccò
    Quantum-Mechanical Modeling of Accumulation Layers in MOS Structures
    IEEE Transactions on Electron Devices
    vol. ED-39, pp. 1732-1739, Jul. , 1992.


    (Ref: 95)

  167. E. Sangiorgi,   M. R. Pinto
    A Semi-empirical Model of Surface Scattering for Monte-Carlo Simulations of Silicon n-MOSFETs
    IEEE Transactions on Electron Devices
    vol. ED-39, pp. 356-361, Feb. , 1992.


    (Ref: 94)

  168. L. Selmi,   D. B. Estreich,   B. Riccò
    Small Signal MMIC Amplifiers with Bridged T-Coil Matching Networks
    IEEE Journal of Solid State Circuits
    Vol. 27, pp. 1093-1096, Jul. , 1992.


    (Ref: 93)

  169. S. Ercolani,   M. Favalli,   M. Damiani,   P. Olivo,   B. Riccò
    Testability Measures in Pseudorandom Testing
    IEEE Transactions on Computer Aided Design
    vol. CAD-11, pp. 794-800, Jun., 1992.


    (Ref: 92)

  170. L. Selmi,   B. Riccò
    Modeling Temperature Effects in the DC I-V Characteristics of GaAs MESFET's
    IEEE Transactions on Electron Devices
    vol. ED-40, pp. 273-277, Feb., 1993.


    (Ref: 116)

  171. L. Selmi,   H. Wong,   E. Sangiorgi,   M. Lanzoni
    Investigation of hot electron luminescence in silicon by means of dual gate MOS structures
    IEEE International Electron Device Meeting (IEDM)
    Washington D.C., pp. 531-534, Dec., 1993.


    (Ref: 149)

  172. L. Selmi,   E. Sangiorgi,   R. Bez,   B. Riccò
    Measurement of hot hole injection probability from Si to SiO2 in p-MOSFETs
    IEEE International Electron Device Meeting (IEDM)
    Washington D.C., pp. 333-336, Dec., 1993.


    (Ref: 148)

  173. M. Lanzoni,   C. Riva,   P. Olivo
    Analysis of FLASH Structures Erased by Ultra-Short Pulses
    ESPRIT Workshop on the Characterization and Growth of Thin Dielectrics in Microelectronics
    Cork (Ireland), Nov., 1993.


    (Ref: 147)

  174. P. Olivo
    Quantum Effects in MOS Thin Dielectric Structures
    ESPRIT Workshop on the Characterization and Growth of Thin Dielectrics in Microelectronics
    Cork (Ireland), Nov., 1993.


    (Ref: 146)

  175. C. Metra,   M. Favalli,   P. Olivo,   B. Riccò
    A Highly Testable 1-out-of-3 CMOS Checher
    IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
    Venezia (Italy), pp. 279-286, Oct., 1993.


    (Ref: 145)

  176. C. Metra,   M. Favalli,   P. Olivo,   B. Riccò
    Design Rules for CMOS Self-Checking Circuits with Parametric faults in the Functional Block
    IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
    Venezia (Italy), pp. 271-278, Oct., 1993.


    (Ref: 144)

  177. M. Favalli,   M. Dalpasso,   P. Olivo,   B. Riccò
    Analysis of Dynamic Effects of Resistive Bridging Faults in CMOS and BiCMOS Digital ICs
    IEEE International Test Conference (ITC)
    Baltimore (Maryland), pp. 865-874, Oct., 1993.


    (Ref: 143)

  178. C. Fiegna,   H. Iwai,   E. Sangiorgi,   B. Riccò
    Analysis of carrier transport and heating in ultra-small SOI n-MOSFETs
    European Solid State Device Research Conference (ESSDERC)
    Grenoble (France), pp. 675-678, Sep., 1993.


    (Ref: 142)

  179. A. Abramo,   R. Brunetti,   C. Jacoboni,   F. Venturi,   E. Sangiorgi
    Monte Carlo simulation of carrier-carrier interaction for silicon devices
    International Conference on Simulation of Semiconductor Devices and Processes (SISDEP)
    Vienna (Austria), pp. 181-184, Sep., 1993.


    (Ref: 141)

  180. C. Fiegna,   H. Iwai,   T. Wada,   T. Saito,   E. Sangiorgi,   B. Riccò
    A new scaling methodology for the 0.1-0.025 micron MOSFET
    Symposium on VLSI Technology
    Kyoto (Japan), pp. 33-34, May., 1993.


    (Ref: 140)

  181. L. Selmi,   C. Fiegna,   E. Sangiorgi,   R. Bez,   B. Riccò
    A study of injection conditions in the substrate hot electron induced degradation of n-MOSFETS
    VPAD
    Nara (Japan), pp. 156-157, May., 1993.


    (Ref: 139)

  182. C. Fiegna,   H. Iwai,   T. Kimura,   S. Nakamura,   E. Sangiorgi,   B. Riccò
    Monte Carlo analysis of hot carrier effects in ultra small geometry MOSFETs
    VPAD
    Nara (Japan), pp. 102-103, May., 1993.


    (Ref: 138)

  183. Y. Tsuboi,   C. Fiegna,   E. Sangiorgi,   B. Riccò,   T. Wada,   Y. Katsumata,   H. Iwai
    Analysis of collector signal delay in bipolar devices using a Monte Carlo method
    VPAD
    Nara (Japan), pp. 98-99, May., 1993.


    (Ref: 137)

  184. C-S Yao,   D. Chen,   R. W. Dutton,   F. Venturi,   E. Sangiorgi,   A. Abramo
    An efficient inpact ionization model for silicon Monte Carlo simulation
    VPAD
    Nara (Japan), pp. 42-43, May., 1993.


    (Ref: 136)

  185. C. Metra,   M. Favalli,   P. Olivo,   B. Riccò
    Testing of Resistive Bridging Faults in CMOS Flip-Flop
    IEEE European Test Conference (ETC)
    Rotterdam (The Netherlands), pp. 530-531, Apr., 1993.


    (Ref: 135)

  186. P. Olivo,   M. Damiani,   B. Riccò
    Aliasing Minimization in Signature Analysis Testing
    IEEE European Test Conference (ETC)
    Rotterdam (The Netherlands), pp. 451-456, Apr., 1993.


    (Ref: 134)

  187. M. Dalpasso,   M. Favalli,   P. Olivo,   B. Riccò
    Influence of IC Synthesis on the Random Pattern Testability of Parametric Bridging Faults
    IEEE European Test Conference (ETC)
    Rotterdam (The Netherlands), pp. 398-407, Apr., 1993.


    (Ref: 133)

  188. E. Sangiorgi,   C. Fiegna,   A. Abramo
    Modeling of High Energy Transport in Silicon by means of the Monte Carlo Method
    SMS
    Taipei (Twiwan), pp. 17-20, Mar., 1993.


    (Ref: 132)

  189. M. Lanzoni,   M. Favalli,   P. Olivo,   B. Riccò
    An Implementation of CMOS Design For Testability Techniques for non Stuck-at faults
    International Conference on Microelectronics Test Structures (ICMTS)
    Sitges (Spain), pp. 95-99, Mar., 1993.


    (Ref: 131)

  190. M. Favalli,   P. Olivo,   B. Riccò
    Testability Measures Combining Probabilistic and Sampling Techniques
    IEEE European Design Automation Conference (EDAC)
    Paris (France), pp. 425-431, Feb., 1993.


    (Ref: 130)

  191. L. Benini,   M. Favalli,   P. Olivo,   B. Riccò
    A Novel Approach to Cost-Effective Estimate of Power in CMOS ICs
    IEEE European Design Automation Conference (EDAC)
    Paris (France), pp. 354-360, Feb., 1993.


    (Ref: 129)

  192. C. Fiegna,   E. Sangiorgi
    Comments on "Determination of Space-Dependent Electron Distribution Function by combined use of Energy and Boltzmann Transport Equation: Improvement, Evaluation and Explanation"
    IEEE Transactions on Electron Devices
    vol. ED-40, pp. 2369-2370, Dec., 1993.


    (Ref: 128)

  193. C. Fiegna,   E. Sangiorgi,   L. Selmi
    Oxide-field Dependence of Electron Injection from Silicon into Silicon Dioxide
    IEEE Transactions on Electron Devices
    vol. ED-40, pp. 2018-2022, Nov., 1993.


    (Ref: 127)

  194. M. Favalli,   M. Dalpasso,   P. Olivo,   B. Riccò
    Analysis of Resistive Bridging Fault Detection in BiCMOS Digital ICs
    IEEE Transactions on VLSI Systems
    vol. 1, pp. 342-355, Sep., 1993.


    (Ref: 126)

  195. M. Dalpasso,   M. Favalli,   P. Olivo,   B. Riccò
    Fault Simulation of Parametric Bridging Faults in CMOS ICs
    IEEE Transactions on Computer Aided Design
    vol. CAD-12, pp. 1403-1410, Sep., 1993.


    (Ref: 125)

  196. A. Abramo,   F. Venturi,   E. Sangiorgi,   J. Higman,   B. Riccò
    A numerical method to compute isotropic band models from anisotropic semiconductor band structures
    IEEE Transactions on Computer Aided Design
    vol. CAD-12, pp. 1327-1335, Sep., 1993.


    (Ref: 124)

  197. M. R. Pinto,   E. Sangiorgi,   J. Bude
    Silicon MOS transconductance scaling into the ovrshoot regime
    IEEE Electron Device Letters
    vol. EDL-14, pp. 375-378, Aug., 1993.


    (Ref: 123)

  198. R. Menozzi,   P. Cova,   L. Selmi
    Experimental Application of a Novel Technique to Extract Gate Bias Dependent Source and Drain Parasitic Resistances of GaAs MESFETs
    Solid State Electronics
    vol. 36, pp. 1083-1084, Jul., 1993.


    (Ref: 122)

  199. L. Selmi,   B. Riccò
    Design of an X-band, Transformer Coupled Amplifier with improved Stability and Layout
    IEEE Journal of Solid State Circuits
    vol. 28, pp. 701-703, Jun., 1993.


    (Ref: 121)

  200. M. Lanzoni,   M. Favalli,   P. Olivo,   B. Riccò
    An Experimental Study of Testing Techniques for Bridging Faults in CMOS ICs
    IEEE Journal of Solid State Circuits
    vol. 28, pp. 686-690, Jun., 1993.


    (Ref: 120)

  201. J. Suñé,   M. Lanzoni,   P. Olivo
    Temperature Dependence of Fowler-Nordheim Injection from Accumulated n-type Silicon into Silicon Dioxide
    IEEE Transactions on Electron Devices
    vol. ED-40, pp. 1017-1019, May., 1993.


    (Ref: 119)

  202. M. Lanzoni,   J. Suñé,   P. Olivo,   B. Riccò
    Advanced Electrical-Level Modeling of EEPROM Cells
    IEEE Transactions on Electron Devices
    vol. ED-40, pp. 951-957, May., 1993.


    (Ref: 118)

  203. C. Fiegna,   E. Sangiorgi
    Modeling of High-Energy Electrons in MOS Devices at the Microscopic Level
    IEEE Transactions on Electron Devices
    vol. ED-40, pp. 619-627, Mar., 1993.


    (Ref: 117)

  204. M. Lanzoni,   L. Briozzo,   B. Riccò
    A Novel Approach to Controlled Programming of Tunnel-Based Floating-Gate
    IEEE Journal of Solid State Circuits
    vol. 29, pp. 151-154, Feb., 1994.


    (Ref: 150)

  205. L. Selmi,   E. Sangiorgi,   R. Bez,   B. Riccò
    A Test Chip and an Accurate Measurement System to Characterize Hot Hole Injection in the Gate Oxide of p-MOSFETs
    IEEE ICMTS
    San Diego (California), p. 68, 1994.


    (Ref: 271)

  206. C. Fiegna,   H. Iwai,   T. Wada,   M. Saito,   E. Sangiorgi,   B. Riccò
    Scaling the MOS Transistor Below 0. 1 micron: Methodology, Structures and Technology RequirementsDevice
    IEEE Transactions on Electron Devices
    vol. ED-41, p. 941, Jun., 1994.


    (Ref: 217)

  207. L. Selmi,   A. Alfieri,   B. Riccò
    AC Frequency Resolved Measurements for Direct Extraction of the Parasitic Resistance of Individual MOSFETs
    IEEE International Electron Device Meeting (IEDM)
    San Francisco, p. 471, Dec., 1994.


    (Ref: 174)

  208. A. Ghetti,   L. Selmi,   E. Sangiorgi,   A. Abramo,   F. Venturi
    A combined transport-injection model for hot-electron and hot-hole injection in the gate oxide of MOS structures
    IEEE International Electron Device Meeting (IEDM)
    San Francisco, p. 363, Dec., 1994.


    (Ref: 173)

  209. C. Fiegna,   H. Iwai,   M. Saito,   E. Sangiorgi
    Application of semiclassical device simulation to trade-off studies for sub-0.1 micron MOSFET
    IEEE International Electron Device Meeting (IEDM)
    San Francisco, Dec., 1994.


    (Ref: 172)

  210. D.Esseni,   L. Selmi,   E. Sangiorgi,   R. Bez,   B. Riccò
    Bias and Temperature Dependence of Gate and Substrate Currents in n-MOSFETs at Low Drain Voltage
    IEEE International Electron Device Meeting (IEDM)
    S.Francisco, p. 307, Dec., 1994.


    (Ref: 171)

  211. C. Metra,   M. Favalli,   B. Riccò
    Highly Testable and Compact 1-out-of-n CMOS Checkers
    International Workshop on Defect and Fault Tolerance in VLSI Systems
    Montreal (Canada), pp. 142-150, Oct., 1994.


    (Ref: 170)

  212. C. Metra,   M. Favalli,   B. Riccò
    CMOS Self Checking Circuits with Faulty Sequential Functional Blocks
    International Workshop on Defect and Fault Tolerance in VLSI Systems
    Montreal (Canada), pp. 133-141, Oct., 1994.


    (Ref: 169)

  213. C. Metra
    Minimal Power-Delay Product CMOS Buffer
    Power and Timing Modeling, Optimization and Simulation (PATMOS)
    Barcellona (Spain), pp. 150-157, Oct., 1994.


    (Ref: 168)

  214. M. Begin,   F. M. Ghannouchi,   F. Beauregard,   L. Selmi,   B. Riccò,   V. Borelli
    Characterization of Transient Effects in the S-Parameters of GaAs MESFETs by means of Pulsed Measurements
    European Solid State Device Research Conference (ESSDERC)
    Edimburgh, p.639, Sep., 1994.


    (Ref: 167)

  215. L. Selmi,   A. Pieracci,   M. Lanzoni,   M. Pavesi,   R. Bez,   E. Sangiorgi
    Experimental Analysis of Polarization in the Hot-Carrier Luminescence of Silicon Devices
    European Solid State Device Research Conference (ESSDERC)
    Edimburgh, p.421, Sep., 1994.


    (Ref: 166)

  216. M. Ono,   M. Saito,   T. Yoshitomi,   C. Fiegna,   T. Ohguro,   H.S. Momose,   H. Iwai
    Influence of High Substrate Doping Concentration on Hot Carrier and other Characteristics of Small-Geometry CMOS Transistors Down to the 0.1 micron Generation
    Symposium on VLSI Technology
    May., 1994.


    (Ref: 165)

  217. M.Begin,   F. M. Ghannouchi,   L. Selmi,   B. Riccò
    Instantaneous S-parameters Measurements of MESFETs under Burst Bias Conditions
    IEEE IMTC Technical Digest
    Hamamatsu (Japan), p.858, May., 1994.


    (Ref: 164)

  218. L. Benini,   M. Favalli,   B. Riccò
    Analysis of hazard contribution to power dissipation in CMOS IC's
    IEEE International Workshop on Low Power Design
    pp. 27-32, May., 1994.


    (Ref: 163)

  219. M. Lanzoni,   L. Selmi,   R. Bez,   M. Manfredi
    A Test Pattern to Investigate the Effect of Capping Layers on the Hot Carrier Induced Photon Spectra of MOSFETs
    International Conference on Microelectronics Test Structures (ICMTS)
    S. Diego (California), pp. 204-207, Mar., 1994.


    (Ref: 162)

  220. M. Favalli,   M. Dalpasso,   P. Olivo,   B. Riccò
    Modeling of Broken Connections Faults in CMOS ICs
    IEEE European Design and Test Conference (ED&TC)
    Paris (France), pp. 159-164, Mar., 1994.


    (Ref: 161)

  221. C. Metra,   M. Favalli,   B. Riccò
    Design of CMOS self-checking sequential circuits with improved detectability of bridging faults
    IEE Electronics Letters
    vol. 30 No.23, pp. 1934-1936, Nov., 1994.


    (Ref: 160)

  222. A. Abramo,   R. Brunetti,   C. Jacoboni,   F. Venturi,   E. Sangiorgi
    A Multi-Band Monte Carlo Approach to Coulomb Interaction for Device Analysis
    Journal of Applied Physics
    vol. 76 No.10, pp. 5786-5794, Nov., 1994.


    (Ref: 159)

  223. P. Olivo,   J. Suñé
    Quantum Effects in Accumulated MOS Thin Dielectrics Structures
    Microelectronics Journal
    vol. 25, pp. 523-532, Oct., 1994.


    (Ref: 158)

  224. M. Lanzoni,   C. Riva,   P. Olivo
    Characterization of Flash Structures Erased with Ultra-Short Pulses
    Microelectronics Journal
    vol. 25, pp. 491-494, Oct., 1994.


    (Ref: 157)

  225. M. Dalpasso,   M. Favalli,   P. Olivo,   J. P. Teixeira
    Realistic Testability Estimates for CMOS IC's
    IEE Electronics Letters
    vol. 30 No.19, p. 1593-1595, Sep., 1994.


    (Ref: 156)

  226. C. Fiegna,   E. Sangiorgi,   L. Selmi
    Reply to: Comments on Oxide field dependence of Electron Injection from Silicon into Silicon Dioxide
    IEEE Transactions on Electron Devices
    vol. ED-41, p.1681, Sep., 1994.


    (Ref: 155)

  227. L. Selmi,   C. Fiegna,   R. Bez
    Correlation between Substrate Hot Electron Energy and Homogeneous Degradation in n-MOSFETs
    IEEE Transactions on Electron Devices
    vol. ED-41, p.1667, Sep., 1994.


    (Ref: 154)

  228. C. Metra,   M. Favalli,   B. Riccò
    Novel 1-out-of-n CMOS checker
    IEE Electronics Letters
    vol. 30, pp. 1398-1400, Aug., 1994.


    (Ref: 153)

  229. C. Metra,   B. Riccò
    Enhanced reliability evaluation for self-checking circuits
    IEE Electronics Letters
    vol. 30, pp. 776-778, May., 1994.


    (Ref: 152)

  230. Y. Tsuboi,   C. Fiegna,   E. Sangiorgi,   B. Riccò,   T. Wada,   Y. Katsumata,   H. Iwai
    Monte Carlo Analysis of Velocity Overshoot Effects in Bipolar Devices with and without an i-Layer
    IEICE Transactions on Electronics
    vol. E77-C, pp. 174-178, Feb., 1994.


    (Ref: 151)

  231. C. Metra,   M. Favalli,   P. Olivo,   B. Riccò
    Design of CMOS Checkers with Improved Testability of Bridging and Transistor Stuck-on Faults
    Journal of Electronic Testing, Theory and Applications
    vol. 6, pp. 7-22, Feb., 1995.


    (Ref: 175)

  232. L. Selmi,   B. Riccò
    Frequency-resolved Measurements for the Characterization of MOSFET Pameters at Low Longitudinal Field
    IEEE Transactions on Electron Devices
    vol. ED-42, p. 315, Apr., 1995.


    (Ref: 218)

  233. B. Riccò,   R. Versari,   D. Esseni
    A Novel Method to Characterize Parasitic Capacitances in MOSFET's
    IEEE Electron Device Letters
    vol. 16, pp. 485-487, Nov., 1995.

    A new technique exploiting the body effect is presented to separate intrinsic from extrinsic capacitances in submicron MOSFET's. The method has been validated using 2-D numerical simulations and results obtained with transistors fabricated with 0.7um technology are presented.
    (Ref: 208)

  234. M. Favalli,   L. Benini
    Analysis of glitch power dissipation in CMOS IC's
    International Symposium on Low Power Design
    pp. 123-128,, 1995.


    (Ref: 206)

  235. M. Favalli,   B. Riccò,   L. Penza
    A Novel DFT technique for critical bridging faults in CMOS and BiCMOS ICs
    IEEE European Design and Test Conference (ED&TC)
    pp. 568-572, Mar., 1995.


    (Ref: 205)

  236. L. Benini,   M. Favalli,   G. De Micheli
    Generalized Matching: a new approach to concurrent logic optimization and library binding
    International Workshop on Logic Synthesis
    , 1995.


    (Ref: 204)

  237. L. Selmi,   M. Pavesi,   H. S. Wong,   A. Acovic,   E. Sangiorgi
    A Comparative Study of Hot-Carrier Induced Light Emission and Degradation in Bulk and Soi MOSFETs
    IEEE International Electron Device Meeting (IEDM)
    Washington DC (USA), Dec., 1995.


    (Ref: 203)

  238. L. Selmi,   M. Mastrapasqua,   D .M. Boulin,   J. D. Bude,   M. Manfredi,   E. Sangiorgi,   M. R. Pinto
    Characterization and Modeling of Hot-Carrier Luminescence in Silicon n+/n/n+ Devices
    IEEE International Electron Device Meeting (IEDM)
    Washington DC (USA), Dec., 1995.


    (Ref: 202)

  239. D. Esseni,   L. Selmi,   R. Bez,   L. Ravazzi,   E. Sangiorgi
    Soft Programming in Scaled FLASH Cells
    European Solid State Device Research Conference (ESSDERC)
    The Hague (The Netherlands), p. 549, 1995.


    (Ref: 201)

  240. A. Ghetti,   X. Wang,   F. Venturi,   F. Leon
    Stability issues in Self-Consistent Monte Carlo-Poisson simulations
    International Conference on Simulation of Semiconductor Devices and Processes (SISDEP)
    Erlangen (Germany), p. 388, Sep., 1995.


    (Ref: 200)

  241. A. Abramo,   C. Fiegna,   F. Venturi
    Hot carrier effects in short MOSFETs at low applied voltages
    IEEE International Electron Device Meeting (IEDM)
    Washington DC (USA), Dec., 1995.


    (Ref: 199)

  242. A. Abramo,   J. Bude,   F. Venturi,   M. R. Pinto,   E. Sangiorgi
    Performance optimization in Si/SiGe heterostructure FETs
    International Conference on Simulation of Semiconductor Devices and Processes (SISDEP)
    Erlangen (Germany), p. 106, Sep., 1995.


    (Ref: 198)

  243. C. Metra,   M. Favalli,   B. Riccò
    Novel Berger Code Checker
    IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
    Lafayette (Louisiana), pp. 287-295, Nov., 1995.


    (Ref: 197)

  244. M. Favalli,   C. Metra
    The Effect of Glitches on Buffer Optimization
    Power And Timing Modeling, Optimization and Simulation Conference (PATMOS)
    Oldenburg (Germany), pp. 202-212, Oct., 1995.


    (Ref: 196)

  245. C. Metra,   M. Favalli,   B. Riccò
    Glitch Power Dissipation Model
    Power And Timing Modeling, Optimization and Simulation Conference (PATMOS)
    Oldenburg (Germany), pp. 175-189, Oct., 1995.


    (Ref: 195)

  246. C. Metra,   M. Favalli,   B. Riccò
    Highly Testable 1-out-of-n Dynamic CMOS Checker
    IEEE International On-Line Testing Workshop
    Nice (France), pp. 248-252, Jul., 1995.


    (Ref: 194)

  247. M. Dalpasso,   M. Favalli,   P. Olivo
    Test Pattern Generation for IDDQ: Increasing Test Quality
    IEEE European Design and Test Conference (ED&TC)
    Paris (France), Mar., 1995.


    (Ref: 193)

  248. M. Dalpasso,   M. Favalli,   P. Olivo
    Correlation between IDDQ Testing Quality and Sensor Accuracy
    IEEE European Design and Test Conference (ED&TC)
    Paris (France), Mar., 1995.


    (Ref: 192)

  249. A. Bogliolo,   M. Damiani,   P. Olivo,   B. Riccò
    Reliability Evaluation of Combinational Logic Circuits by Symbolic Simulation
    IEEE VLSI Test Symposium
    Princeton (N.J), Apr., 1995.


    (Ref: 191)

  250. A. Bogliolo,   M. Damiani
    Synthesis of Multilevel Fault-Tolerant Combinational Circuits
    IEEE European Design and Test Conference (ED&TC)
    Paris (France), Mar., 1995.


    (Ref: 190)

  251. A. Bogliolo,   M. Damiani
    Synthesis of Combinational Circuits with Special Fault-Handling Capabilities
    IEEE VLSI Test Symposium
    Princeton (N.J), Apr., 1995.


    (Ref: 189)

  252. A. Bogliolo,   L. Benini,   G. De Micheli,   B. Riccò
    Accurate Logic Level Power Estimation
    IEEE Symposium on Low Power Electronics
    San Jose (California), 1995.


    (Ref: 188)

  253. M. Favalli,   B. Riccò
    A novel DFT technique for Comprehensive Testing of CMOS buffers
    Alta Frequenza - Rivista di Elettronica
    vol. 7 No.2, pp. 78-80, , 1995.


    (Ref: 187)

  254. C. Fiegna,   L. Selmi
    Problemi della Ricerca sulle Tecnologie CMOS
    Alta Frequenza - Rivista di Elettronica
    vol. 7 no.1, pp. 25-32, Mar., 1995.


    (Ref: 186)

  255. D. Esseni,   L. Selmi,   E. Sangiorgi,   R. Bez,   B. Riccò
    Temperature Dependence of Gate and Substrate Currents in the CHE Crossover Regime
    IEEE Electron Device Letters
    vol. EDL-16 no.11, Nov., 1995.


    (Ref: 185)

  256. L. Selmi,   E. Sangiorgi,   R. Bez
    Non-Local Effects in p-MOSFET Substrate Hot Hole Injection Experiments
    IEEE Electron Device Letters
    vol. EDL-16 no.10, p. 442, Oct., 1995.


    (Ref: 184)

  257. L. Selmi
    Silicon Luminescence Techniques for the Characterization of Hot-Carrier and Degradation Phenomena in MOS Devices
    Microelectronic Engineering
    vol. 28 N.1, p. 250, Jun., 1995.


    (Ref: 183)

  258. M. Ono,   M. Saito,   T. Yoshitomi,   C. Fiegna,   T. Ohguro,   H. Iwai
    A 40 nm Gate Length n-MOSFET
    IEEE Transactions on Electron Devices
    vol. TED 42 No.10, pp. 1822-1830, Oct., 1995.


    (Ref: 182)

  259. M. Ono,   M. Saito,   T. Yoshitomi,   C. Fiegna,   T. Ohguro,   H. Sasaki Momose,   H. Iwai
    A study on Hot Carrier effects on N-MOSFET's under high substrate impurity concentration
    IEEE Transactions on Electron Devices
    vol. TED 42 No.8, p. 1510, Aug., 1995.


    (Ref: 181)

  260. M. Ono,   M. Saito,   T. Yoshitomi,   C. Fiegna,   T. Ohguro,   H. Sasaki Momose,   H. Iwai
    Fabrication of sub-50-nm gate length n-metal-oxide-semiconductor field effect transistors and their electrical characteristics
    Journal of Vacuum Science Technology
    vol. 13 No.4, p. 1740, Jul./Aug., 1995.


    (Ref: 180)

  261. B. Neri,   P. Olivo,   R. Saletti,   M. Signoretta
    Dielectric Breakdown and Reliability of MOS Microstructures: Traditional Characterization and Low-Frequency Noise Measurements
    Microelectronics and Reliability
    , 1995.


    (Ref: 179)

  262. M. Lanzoni,   B. Riccò
    Experimental Characterization of circuits for Controlled Programming of Floating-Gate MOSFETs
    IEEE Journal of Solid State Circuits
    Feb., 1995.


    (Ref: 178)

  263. C. Metra,   M. Favalli
    Novel 1-out-of-n Dynamic CMOS Checker
    IEE Electronics Letters
    vol. 31, Nov., 1995.


    (Ref: 177)

  264. C. Metra,   M. Favalli,   B. Riccò
    Design of TSC CMOS Checkers for any 1-out-of-n Code
    Journal of Microelectronic Systems Integration
    vol. 3 No.2, pp. 81-91, 1995.


    (Ref: 176)

  265. M. Lanzoni,   G. Tondi,   P. Galbiati,   B. Riccò
    Non-Volatile EEPROM Cells for Analog Circuit Calibration
    European Solid State Device Research Conference (ESSDERC)
    Bologna (Italy), pp. 135-138, Sep., 1996.


    (Ref: 207)

  266. P. Vuillod,   L. Benini,   A. Bogliolo,   G. De Micheli
    Clock-skew optimization for peak current reduction
    International Symposium on Low-Power Electronics and Design (ISLPED)
    Monterey (USA), pp. 265-270, Aug., 1996.


    (Ref: 325)

  267. A. Bogliolo,   L. Benini,   G. De Micheli,   B. Riccó
    Gate-level current waveform simulation of cmos integrated circuits
    International Symposium on Low-Power Electronics and Design (ISLPED)
    Monterey (USA), pp. 109-112, Aug., 1996.


    (Ref: 324)

  268. A. Bogliolo,   L. Benini,   D. Guan,   D. Ku,   G. De Micheli
    Open Distributed EDA Environments on the Web
    Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)
    , pp. 47-54, Nov., 1996.


    (Ref: 323)

  269. L. Benini,   A. Bogliolo,   G. De Micheli
    Distributed EDA tool integration: the PPP paradigm
    IEEE International Conference on Computer Design (ICCD)
    Austin (USA), pp. 448-453, Oct., 1996.


    (Ref: 322)

  270. A. Bogliolo,   L. Benini,   G. De Micheli
    Power Estimation of Cell-Based CMOS Circuits
    ACM Design Automation Conference (DAC)
    Las Vegas (USA), pp. 433-438, Jun., 1996.


    (Ref: 321)

  271. C. Metra,   J-C. Lo
    Compact and High Speed Berger Code Checker
    IEEE International On-Line Testing Workshop
    St. Jean de Luz (France), pp. 144-149, Jul., 1996.


    (Ref: 287)

  272. L. Benini,   A. Bogliolo,   M. Favalli,   G. De Micheli
    Regression models for behavioral power estimation
    Power, Timing Modeling Optimization and Simulation (PATMOS)
    Bologna (It), pp. 179-187, Sep., 1996.


    (Ref: 285)

  273. M. Favalli,   L. Benini,   G. De Micheli
    Design for testability of gated clock FSMs
    IEEE European Design and Test Conference (ED&TC)
    Paris (Fr), pp. 589-596, Mar., 1996.


    (Ref: 284)

  274. M. Favalli,   M. Dalpasso,   P. Olivo
    Modeling and Simulation of Broken Connections in CMOS ICs
    IEEE Transactions on Computer Aided Design
    vol. 5, n. 7, pp. 808-814, Jul., 1996.


    (Ref: 283)

  275. C. Metra,   M. Favalli,   B. Riccò
    Compact and Highly Testable Error Indicator for Self-Checking Circuits
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
    Boston (USA), pp. 204-212, Nov., 1996.


    (Ref: 275)

  276. C. Metra,   M. Favalli,   B. Riccò
    Tree Checkers for Applications with Low Power-Delay Requirements
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
    Boston (MA), p. 213 - 220, Nov.,, 1996.


    (Ref: 274)

  277. C. Metra,   M. Favalli,   B. Riccò
    Embedded 1-out-of-3 Checkers with On-Line Testing Capability
    IEEE International On-Line Testing Workshop
    St. Jean de Luz (France), p. 136 - 141, Jul., , 1996.


    (Ref: 273)

  278. C. Metra,   M. Favalli,   B. Riccò
    Embedded Two-Rail Checkers with On-Line Testing Ability
    IEEE VLSI Test Symposium
    Monterey (CA), p. 145 - 150, Apr.,, 1996.


    (Ref: 272)

  279. M. Begin,   F. M. Ghannouchi,   F. Beauregard,   L. Selmi,   B. Riccò
    Characterization of the Transient Behavior of a GaAs MESFET Using Dynamic I-V and S-parameter Measurements
    IEEE Transactions on Instrumentation and Measurements
    vol. 45, p. 231, 1996.


    (Ref: 253)

  280. M. Dalpasso,   M. Favalli,   P. Olivo
    IDDQ test invalidation by break faults
    IEE Electronic Letters
    vol. 32, n. 11, pp. 944-946, , 1996.


    (Ref: 215)

  281. M. Favalli,   C. Metra
    Sensing circuit on-line detection of delay faults
    IEEE Transactions on VLSI Systems
    vol. 4, n. 1, pp. 130-133, Mar., 1996.

    A sensing circuit for on-line testing of delay faults is presented. It can be used to monitor the outputs of circuits that are either general, or designed to be self-checking with respect to steady state errors. Detailed analyses of the proposed circuit have shown that it is preferable to alternate solutions from the point of view of both the accuracy and the self-testing capability that make it suitable for self-checking applications. Checking architectures for delay faults, making use of the proposed sensing circuit and of standard checkers, are presented.
    (Ref: 213)

  282. B. Riccò,   R. Versari,   D. Esseni
    Characterization of Polysilicon-Gate Depletion in MOS Structures
    IEEE Electron Device Letters
    vol. 17, pp. 103-106, Mar., 1996.

    This paper presents a new technique to characterize the depletion capacitance and (active) impurity concentration of gate polysilicon in MOS transistors. The method has been validated by means of 2-D simulation; experimental results obtained with state-of-the-art n-channel 0.5 micrometer transistors are presented.
    (Ref: 210)

  283. A. Pieracci,   M. Lanzoni,   P. Galbiati,   S. Manzini,   C. Contiero,   B. Riccò
    Extraction of Channel Doping Profile in DMOS Transistors
    IEEE International Electron Device Meeting (IEDM)
    San Francisco CA (USA), pp. 485-488, Dec., 1996.

    This paper presents the first method to characterize the doping profile and the length of the channel of double-diffused MOS transistors, typically used in smart power ICs. The method, based on capacitance measurements, is validated by means of 2D numerical simulation and applied to transistors fabricated with advanced 0.6um technology.
    (Ref: 209)

  284. B. Riccò,   G. Tondi,   M. Lanzoni
    Extraction of Oxide Thickness from Harmonic Distortion of Displacement Currents in MOS Capacitors
    IEEE Transactions on Electron Devices
    vol. 44, pp. 1552-1554, Sep., 1997.

    This brief presents a new experimental technique to determine the thickness of (thin) insulator films from the analysis of the harmonic distortion of the displacement current due to the nonlinearity of the C-V characteristics of MOS capacitors. Such a method substantially improves the state of the art, as it overcomes the noise problem affecting a previous technique, particularly suitable for thin insulators since it operates in the virtual absence of tunneling current and other complex phenomena.
    (Ref: 211)

  285. L. Benini,   G. De Micheli,   E. Macii,   D. Sciuto,   C. Silvano
    Asymptotic Zero-Transition Activity Encoding for in Low-Power Microprocessor-Based SystemsAddress Busses
    IEEE/ACM Great Lakes Symposium on VLSI (GLS)
    Urbana (USA), pp. 77-82, Mar., 1997.


    (Ref: 315)

  286. L. Benini,   E. Macii,   M. Poncino
    Efficient Controller Design for Telescopic Units
    IEEE International Conference on Innovative System in Silicon (ISIS)
    Austin (USA), pp. 290-299, Oct., 1997.


    (Ref: 314)

  287. L. Benini,   G. De Micheli,   E. Macii,   M. Poncino,   R. Scarsi
    Quick Generation of Temporal Power Waveforms for RT-Level Hard Macros
    IEEE International Conference on Innovative System in Silicon (ISIS)
    Austin (USA), pp. 331-337, Oct., 1997.


    (Ref: 313)

  288. L. Selmi,   A. Ghetti,   R. Bez,   E. Sangiorgi
    Trade-offs between tunneling and Hot-Carrier Injection in short channel Floating Gate MOSFETs
    Microelectronics Engineering
    vol. 36, pp. 293-296, Jun., 1997.


    (Ref: 312)

  289. B. Fischer,   A. Ghetti,   L. Selmi,   R. Bez,   E. Sangiorgi
    Bias and Temperature Dependence of Homogeneous Hot-Electron Injection from Silicon into Silicon Dioxide at Low Voltages
    IEEE Transactions on Electron Devices
    vol. TED-44, pp. 288-296, Feb., 1997.


    (Ref: 311)

  290. L. Benini,   G. De Micheli
    Dynamic Power Management of Electronic Circuits and Systems
    Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)
    Japan, pp. 3-10, Dec., 1997.


    (Ref: 310)

  291. L. Benini,   G. De Micheli,   E. Macii,   M. Poncino,   R. Scarsi
    Integrating Logic-level Power Management Techniques
    Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)
    Japan, pp. 59-65, Dec., 1997.


    (Ref: 309)

  292. A. Bogliolo,   L. Benini,   G. De Micheli
    Adaptive Least Mean Square behavioral power modeling
    IEEE European Design and Test Conference (ED&TC)
    Paris (France), pp. 404-410, Mar., 1997.


    (Ref: 308)

  293. L. Benini,   G. De Micheli,   E. Macii,   M. Poncino,   R. Scarsi
    Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks
    IEEE European Design and Test Conference (ED&TC)
    Paris (France), pp. 514-528, Mar., 1997.


    (Ref: 307)

  294. L. Benini,   E. Macii,   M. Poncino
    Telescopic Units: increasing the average throughput of pipelined designs by adaptive latency control
    ACM Design Automation Conference (DAC)
    San Jose (USA), pp. 22-27, Jul., 1997.


    (Ref: 306)

  295. L. Benini,   G. De Micheli,   E. Macii,   M. Poncino,   S. Quer
    System-Level Power Optimization of Special Purpose Applications:The Beach Solution
    International Symposium on Low-Power Electronics and Design (ISLPED)
    Monterey (USA), pp. 24-29, Aug., 1997.


    (Ref: 305)

  296. P. Vuillod,   L. Benini,   G. De Micheli
    Re-mapping for low power under tight timing constraints
    International Symposium on Low-Power Electronics and Design (ISLPED)
    Monterey (USA), pp. 287-292, Aug., 1997.


    (Ref: 304)

  297. L. Benini,   G. De Micheli,   E. Macii,   M. Poncino,   R. Scarsi
    Fast power estimation for deterministic input streams
    IEEE International Conference on Computer Aided Design (ICCAD)
    San Jose (USA), pp. 494-501, Nov., 1997.


    (Ref: 303)

  298. P. Vuillod,   L. Benini,   G. De Micheli
    Generalized matching from theory to application
    IEEE International Conference on Computer Aided Design (ICCAD)
    San Jose (USA), pp. 13-20, Nov., 1997.


    (Ref: 302)

  299. L. Benini,   G. De Micheli
    A survey of Boolean matching techniques for library binding
    ACM Transactions on Design Automation of Electronic Systems (TODAES)
    vol. 2, pp. 193-226, Jul., 1997.


    (Ref: 301)

  300. M. Dalpasso,   M. Favalli
    A Method for Increasing the IDDQ Testability
    IEEE Transactions on Computer Aided Design
    vol. 16, no. 10, pp. 1186-1188, Oct., 1997.


    (Ref: 300)

  301. L. Benini,   P. Vuillod,   A. Bogliolo,   G. De Micheli
    Clock-skew Optimization for Peak Current Reduction
    Kluwer Journal of VLSI Signal Processing
    vol. 16, pp. 117-130, Jun., 1997.


    (Ref: 299)

  302. A. Bogliolo,   L. Benini,   G. De Micheli,   B. Riccò
    Power and Current Estimation of Cell-Based CMOS Circuits
    IEEE Transactions on VLSI Systems
    vol. 5, pp. 473-488, Dec., 1997.


    (Ref: 298)

  303. C. Metra,   M. Favalli,   B. Riccò
    On-Line Self-Testing Voting and Detecting Schemes for TMR Systems
    Journal of Microelectronic Systems Integration
    vol. 5, no. 4, pp. 261-273, Dec., 1997.


    (Ref: 291)

  304. C. Metra,   M. Favalli,   P. Olivo,   B. Riccò
    On-Line Detection of Bridging and Delay Faults in Functional Blocks of CMOS Self-Checking Circuits
    IEEE Transactions on Computer Aided Design
    vol. 16, no. 7, pp. 770-776, Jul., 1997.


    (Ref: 290)

  305. R. Versari,   A. Pieracci,   S. Manzini,   C. Contiero,   B. Riccò
    Hot-Carrier Reliability in Submicrometer LDMOS Transistors
    IEEE International Electron Device Meeting (IEDM)
    Washington DC (USA), pp. 371-374, Dec., 1997.

    This paper provides a physical basis for the experimentally determined hot-electron-limited safe operating area of submicrometer LDMOS transistors under static bias conditions. The physical interpretation of the device behavior is based on the analysis of the bias-dependent Gate and Substrate currents and of the relative induced degradation
    (Ref: 289)

  306. Y-Y. Guo,   J-C. Lo,   C. Metra
    Fast and Area-Time Efficient Berger Code Checkers
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
    New York City (USA), pp. 110-118, Nov., 1997.


    (Ref: 288)

  307. C. Metra
    Design Technique for Embedded 1-out-of-3 Checkers
    Alta Frequenza - Rivista di Elettronica
    vol. 9, pp. 68-70, Jan., 1997.


    (Ref: 286)

  308. M. Favalli,   C. Metra
    Leakage Power Reduction for Reactive Computation
    Power and Timing, Modeling, Optimization, Simulation (PATMOS)
    Leuven-la-Neuve, pp. 57-66, Sep., 1997.


    (Ref: 282)

  309. M. Favalli,   M. Dalpasso
    Symbolic handling of bridging fault effects
    Journal of Electronic Testing, Theory and Applications
    vol. 10, n. 3, pp. 271-276, Jun., 1997.


    (Ref: 281)

  310. C. Metra,   M. Favalli,   B. Riccò
    Compact and Low Power Self-Checking Voting Scheme
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
    Paris (France), pp. 137-145, Oct., 1997.


    (Ref: 280)

  311. C. Metra,   M. Favalli,   B. Riccò
    On-Line Testing Scheme for Clocks' Faults
    IEEE International Test Conference (ITC)
    Washington D.C. (USA), pp. 587-596, Oct., 1997.


    (Ref: 279)

  312. C. Metra,   M. Favalli,   B. Riccò
    Self-Checking Detector for Simultaneous On-Line Test of Clock Signals
    IEEE International On-Line Testing Workshop
    Crete (Greece), pp. 79-83, Jul., 1997.


    (Ref: 278)

  313. C. Metra,   M. Favalli,   B. Riccò
    Novel Single Output 1-out-of-3 Code Checker
    IEEE International On-Line Testing Workshop
    Crete (Greece), pp. 228-232, Jul., 1997.


    (Ref: 277)

  314. C. Metra,   M. Favalli,   B. Riccò
    Highly Testable and Compact Single Output Comparator
    IEEE VLSI Test Symposium
    Monterey (California), pp. 210-215, Apr., 1997.


    (Ref: 276)

  315. C. Metra,   M. Favalli,   B. Riccò
    1-out-of-3 Code Checker with Single Output
    IEE Electronics Letters
    vol. 33, p. 1373, 1997.


    (Ref: 254)

  316. M. Favalli,   C. Metra
    Design of Low-Power CMOS Two-Rail Checkers
    Journal of Microelectronic Systems Integration
    vol. 5, n. 2, pp. 101-110, Jun., 1997.

    This paper presents a novel technique for the reduction of power dissipation in tree-structured two-rail checkers. Such technique exploits the properties of this kind of circuits to perform a level by level power minimization, based on functional or statistic informations on the functional unit outputs. During power minimization the algorithm does not introduce undetectable faults, thus it avoid checker testability degradations. The algorithm has been implemented and power dissipation results are shown for a set of benchmarks.
    (Ref: 216)

  317. M. Favalli,   C. Metra
    Testing scheme for IC's clock
    IEEE European Design and Test Conference (ED&TC)
    Paris (Fr), pp. 445-449, Mar., 1997.

    This paper proposes a testing scheme to detect abnormal skews between clock signals inside digital synchronous ICs. The scheme is based on a new CMOS sensing circuit whose compactness and testability with respect to a large set of failures make it suitable for both off-line and on-line testing.
    (Ref: 214)

  318. M. Favalli,   C. Metra
    Low-level Error Recovery Mechanism for Self-Checking Sequential Circuits
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
    Paris (Fr), pp. 234-242, Oct., 1997.

    To match the reliability requirements of small embedded systems, a design methodology is proposed that provides some fault tolerant capabilities to self-checking sequential circuits. By means of simple modifications, such circuits are made fault tolerant with respect to transient, cross-talk and delay faults, while they maintain their self-checking capabilities with respect to permanent faults. The method requires a small area overhead and may also provide some benefit from the yield point of view.
    (Ref: 212)

  319. C. Metra,   M. Favalli,   B. Riccò
    Highly Testable and Compact 1-out-of-n Code Checker with Single Output
    IEEE European Design and Test Conference (ED&TC)
    Paris (France), pp. 981-982, Feb., 1998.


    (Ref: 295)

  320. C. Metra,   M. Favalli,   B. Riccò
    Concurrent Checking of Clock Signal Correctness
    IEEE Design&Test of Computers
    pp. 42-48, Oct., 1998.

    Traditional concurrent-checking techniques may not detect the occurrence of the transient faults and resulting errors likely to affect clock signals in VLSI systems. The authors present a new method and slef-checking circuit implementation for concurrently checking the correctness of clock distribution network signals in synchronous systems.
    (Ref: 335)

  321. R. Versari,   B. Riccò
    Scaling of maximum capacitance of MOSFET with ultra-thin oxide.
    IEE Electronics Letters
    vol. EL-34, pp. 2175-2176, Oct., 1998.

    The maximum capacitance of a polysilicon-gate MOSFET against oxide thickness is studied for different gate and substrate doping levels. It is found that substrate doping contributes to transistor capacitance degradation, imposing a limit on the lower voltage operation for sub-0. 1um CMOS technologies.
    (Ref: 334)

  322. D. Esseni,   A. Pieracci,   M. Quadrelli,   B. Riccò
    Hot Carrier Induced Alterations of MOSFET Capacitances: A Quantitative Monitor for Electrical Degradation.
    IEEE Transactions on Electron Devices
    vol. 45, pp. 2319-2328, Nov., 1998.

    In this paper, combined gate-to-channel (CGSD) and gate-to-bulk (CGB) capacitance measurements are used in order to extract quantitative information about hot-carrier degradation in MOS transistors. An analytical model, explaining the results of accelerated degradation experiments, is presented to establish a simple relationship between CGSD and CGB changes and the stress induced charges Qox and Qit trapped in the oxide or in interface states, respectively. A method, validated by means of 2D numerical simulations, is proposed to determine Qox and Qit directly from the measured capacitances, and is applied to experimental data. The new technique considerably improves the capabilities of previous capacitive methods because it can yield a quantitative determination of Qox and Qit.
    (Ref: 333)

  323. A. Pieracci,   B. Riccò
    A New Characterization Method for Hot-Carrier Degradation in DMOS Transistors
    IEEE Transactions on Electron Devices
    vol. 45, pp. 1855-1858, Aug., 1998.

    This paper presents an original method based on capacitance measurements, that is able to localize and estimate hot-electrons-induced oxide charge in double-diffused MOS (DMOS) transistors. The method is validated by means of two-dimensional (2-D) numerical simulation. Preliminary results obtained with state-of-the-art devices are presented as example of application.
    (Ref: 332)

  324. S. D'Angelo,   C. Metra,   S. Pastore,   A. Pogutz,   G. R. Sechi
    Fault-Tolerant Voting Mechanism and Recovery Scheme for TMR FPGA-based Systems
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
    Austin (Texas), pp. 233-240, Nov., 1998.

    This paper presents an original approach to the implementation of a fault-tolerant FPGA-based system.
    (Ref: 331)

  325. C. Metra,   M. Favalli,   B. Riccò
    Signal Coding Technique and CMOS Gates for Strongly Fault-Secure Combinational Functional Blocks
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
    Austin (Texas), pp. 174-182, Nov., 1998.

    This paper proposes a signal coding technique (using frequency redundancy) and CMOS gates to allow the design of functional blocks of self-checking circuits whose correct operation is guaranteed with respect to a wide set of possible, internal faults. These include not only conventional stuck-ats, but also transistor stuck-ons, transistor stuck-opens and resistive bridgings. Compared to the alternative, existing solution, the technique proposed here does not imply any critical constraint on the circuit electrical parameters. Hence it is better suited to the design of next generation, deep submicron technology circuits.
    (Ref: 330)

  326. C. Metra,   M. Favalli,   B. Riccò
    On-Line Detection of Logic Errors due to Crosstalk, Delay, and Transient Faults
    IEEE International Test Conference (ITC)
    Washington, DC (USA), pp. 524-533, Oct., 1998.

    This paper analyses the problem of systems' on-line testing with respect to logic errors due to crosstalk, delay and transient faults. In particular, we show that logic errors due to crosstalk noise between internal, adjacent lines may be not on-line detectable by conventional concurrent error detection techniques using error detecting codes. Hence, a detector is proposed that allows the on-line detection of such logic errors, and that is self-checking with respect to a wide set of possible internal faults representative of realistic failures, including crosstalk, delay, and transient faults.
    (Ref: 329)

  327. A. Bogliolo,   L. Benini,   G. De Micheli
    Characterization-Free Behavioral Power Modeling
    IEEE Design and Test in Europe Conference (DATE)
    Paris (FR), pp. 767-773, Mar., 1998.


    (Ref: 328)

  328. L. Benini,   A. Bogliolo,   S. Cavallucci,   B. Riccò
    Monitoring System Activity for OS-Directed Dynamic Power Management
    International Symposium on Low-Power Electronics and Design (ISLPED)
    Monterey (USA), Aug., 1998.


    (Ref: 327)

  329. G. A. Paleologo,   L. Benini,   A. Bogliolo,   G. De Micheli
    Policy Optimization for Dynamic Power Management
    ACM Design Automation Conference (DAC)
    San Francisco (USA), pp. 182-187, Jun., 1998.


    (Ref: 326)

  330. L. Benini,   A. Bogliolo,   M. Favalli,   G. De Micheli
    Regression models for behavioral power estimation
    Integrated Computer-Aided Engineering
    vol. 5, pp. 95-106, Feb., 1998.


    (Ref: 320)

  331. D. Esseni,   H. Iwai,   M. Saito,   B. Riccò
    Nonscaling of MOSFET's Linear Resistance in the Deep Submicron Regime
    IEEE Electron Device Letters
    vol. EDL-19, pp. 131-133, Apr., 1998.


    (Ref: 319)

  332. B. Riccò,   G. Gozzi,   M. Lanzoni
    Modeling and Simulation of Stress-Induced Leakage Current in Ultrathin SiO2 Films
    IEEE Transactions on Electron Devices
    vol. ED 45, pp. 1554-1556, Jul., 1998.

    This paper presents a new model for stress-induced leakage current (SILC) in ultrathin SiO2 films, that is able to explain and accurately represent the experimental data obtained with MOS capacitors fabricated with different technologies and oxide thikcness in the 3- 7 nm range.
    (Ref: 318)

  333. C. Metra,   J.-C. Lo
    General Design Method for VLSI High Speed Berger Code Checkers
    IEEE International On-Line Testing Workshop
    Capri (Italy), pp. 177-181, Jul., 1998.

    We propose a general design method for VLSI high speed Berger code checkers, with any number of input bits. Our method can be applied to any existing, conventional Berger code checker design to allow significant improvements of speed, without altering its Totally Self-Checking or Strongly Code-Disjoint property.
    (Ref: 317)

  334. C. Metra,   M. Favalli,   B. Riccò
    Novel Implementation for Highly Testable Parity Code Checkers
    IEEE International On-Line Testing Workshop
    Capri (Italy), pp. 167-171, Jul., 1998.

    This paper proposes a novel CMOS implementation of single output, as well as two output, possibly embedded, parity code checkers, that are Totally Self-Checking or Strongly Code-Disjoint with respect to all possible internal node stuck-ats, transistor stuck-ons, transistor stuck-opens and resistive bridgings. These characteristics are not paid in terms of area overhead, speed and power consumption compared to more conventional solutions.
    (Ref: 316)

  335. M. Lanzoni,   G. Tondi,   P. Galbiati,   B. Riccò
    Automatic and Continuous Offset Compensation of MOS Operational-Amplifiers Using Floating-Gate Transistors
    IEEE Journal of Solid State Circuits
    vol. 33 n. 2, pp. 287-290, Feb., 1998.

    This paper presents a new approach that exploits floating-gate MOS transistors and a feedback control loop to automatically compensate the offset of MOS operational amplifiers in a continuous manner that substantially improves the state of the art in the field. The proposed method can be repeatedly used to compensate the effects of environmental and device modifications, while the possibility to accurately program an arbitrary value of the offset can be exploited to realize high performance and/or programmable comparators and A/D converters.
    (Ref: 297)

  336. C. Metra,   G. Mojoli,   S. Pastore,   D. Salvi,   G. Sechi
    Novel Technique for Testing FPGAs
    IEEE European Design and Test Conference (ED&TC)
    Paris (France), pp. 89-94, Feb., 1998.


    (Ref: 296)

  337. C. Metra
    Majority Logic
    The Encyclopedia of Electrical and Electronic Engineering (Wiley & Sons, NY)
    vol. 12, pp. 317-322, Feb., 1999.


    (Ref: 336)