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Microelectronics Research Group Events

Events 2005

Addressing MPSoC HW/SW platform Challenges (SEM-257)


Speaker:
Luca Benini
DEIS Università di Bologna

Date: 4 February 2005 at 2:00 PM

Location: IMEC auditorium

Abstract.

With the fast diffusion MPSoCs platforms in many application areas, we need a coherent and sinergistic hardware-software approaches and mature design technology to fully exploit their hugepotential. In this talk I will give an overview of recent research and development activity carried out in these areas at the University of Bologna. I will focus primarily on two areas of active development. First, I will survey recent advances in our MPSoC Simulation and Emulation Platform. Second, I will discuss some new results on application parallelization and architectural support forcommunication. Finally, I will give an overview of future developments and cooperation opportunities.

Link

 

SEMINARIO
DI
INFORMAZIONE AZIENDALE presso la Facolta' di Ingegneria - GENOVA

Lunedì 6 giugno 2005 alle ore 11:00

Prof. Bruno Riccò
e Dott.ssa Elisabetta Farella

Dalla ricerca al mercato: percorso difficile ma obbligato
L’intervento affronterà i seguenti argomenti:
• Motivazioni e organizzazione della ricerca accademica
• Esempi di progetti di ricerca: ambient intelligence, microarrays per
riconoscimento di DNA
• La difficile strada verso il mercato

Link

Lecture at EPFL, Losanne

Luca Benini

Date: Thursday-Jul 07, 2005
Time: 10:15-11:15

 

Advanced Networks on chip: architectures and design flow

Link

Lecture at MPSoC Tuesday July 12

NoCs: pushing toward the back-end

by Luca Benini

at the 5th International Forum on Application-Specific Multi-Processor SoC
11 - 15 July 2005, Relais de Margaux, France

Abstract.

Network-on-chips are gaining momentum as the interonnection fabric for fabric of choice for future MPSoCs. Architectural scalability trends and design technology arguments are favorable to the NoC approach, but designers want hard facts and they need solutions that do not require disruptive changes in design technology. In this talk we will look into the experience and lessons learned in developing a complete back-end flow for NoC deployment in current real-life silicon technology.

Link

SBCCI 2005
18th SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN
Chip on the Island

Florianópolis - Brazil
September 4-7, 2005
INVITED TALK #1
Energy efficient NoC design

by Luca Benini
DEIS Università di Bologna, Italy

Abstract

Energy efficiency is a key concern in the design of advanced SoC platforms. In this talk we will explore the delicate interplay between on-chip communication and power consumption. We will move from state-of-the art communication fabrics (shared buses, crossbars), to advanced, "revolutionary" network-on-chip interconnects. We will touch upon several energy optimization and management problems emerging in the design and tuning of on-chip interconnects. Our analysis will show that energy-efficient on-chip communication is one of the cornestones of system-level energy optimization.

Link

   

 

 

Seminari 2004

All'interno del corso di Metodologie di Progettazione Hardware-Software si sono svolti diversi seminari.

 



     

 

 



Micrel Lab @ DEIS - Dipertimento di Elettronica, Informatica e Sistemistica - Facoltà di Ingegneria - Università di Bologna - Viale Risorgimento 2 40136- Bologna - fax 0512093785 - tel 0512093782