| D.E.I.S. - UNIVERSITA' DI BOLOGNA |
|---|
| Dipartimento di Elettronica, Informatica e Sistemistica |
| Home | About | People | Research | Teaching & Thesis | Events & News | Publications | Links | Contacts |
 |
Microelectronics Research Group Events |  |
Events 2005
|
Addressing MPSoC HW/SW platform Challenges (SEM-257)
Date: 4 February 2005 at 2:00 PM Location: IMEC auditorium |
Abstract. With the fast diffusion MPSoCs platforms in many application areas, we need a coherent and sinergistic hardware-software approaches and mature design technology to fully exploit their hugepotential. In this talk I will give an overview of recent research and development activity carried out in these areas at the University of Bologna. I will focus primarily on two areas of active development. First, I will survey recent advances in our MPSoC Simulation and Emulation Platform. Second, I will discuss some new results on application parallelization and architectural support forcommunication. Finally, I will give an overview of future developments and cooperation opportunities.
|
|
SEMINARIO Lunedì 6 giugno 2005 alle ore 11:00 Prof. Bruno Riccò |
Dalla ricerca al mercato: percorso difficile ma obbligato |
|
Lecture at EPFL, Losanne Luca Benini Date: Thursday-Jul 07, 2005
|
Advanced Networks on chip: architectures and design flow |
|
Lecture at MPSoC Tuesday July 12 NoCs: pushing toward the back-end by Luca Benini at the 5th International Forum on Application-Specific Multi-Processor
SoC |
Abstract. Network-on-chips are gaining momentum as the interonnection fabric for fabric of choice for future MPSoCs. Architectural scalability trends and design technology arguments are favorable to the NoC approach, but designers want hard facts and they need solutions that do not require disruptive changes in design technology. In this talk we will look into the experience and lessons learned in developing a complete back-end flow for NoC deployment in current real-life silicon technology. |
| SBCCI 2005 18th SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN Chip on the Island Florianópolis - Brazil by Luca Benini |
Abstract Energy efficiency is a key concern in the design of advanced SoC platforms. In this talk we will explore the delicate interplay between on-chip communication and power consumption. We will move from state-of-the art communication fabrics (shared buses, crossbars), to advanced, "revolutionary" network-on-chip interconnects. We will touch upon several energy optimization and management problems emerging in the design and tuning of on-chip interconnects. Our analysis will show that energy-efficient on-chip communication is one of the cornestones of system-level energy optimization. |
Seminari 2004
All'interno del corso di Metodologie di Progettazione Hardware-Software si sono svolti diversi seminari.
|
|
