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[     Micrel Group - Research     ]
M P A R M . i s
MPARM . project
MPARM is a multi-processor cycle-accurate architectural simulator. Its purpose is the system-level analysis of design tradeoffs in the usage of different processors, interconnects, memory hierarchies and other devices.
MPARM output includes accurate profiling of system performance, execution traces, signal waveforms, and, for many modules, power estimation. The OCP 2.0 point-to-point link is being deployed to connect system components. The MPARM platform includes hardware components (see below) and software components. Currently, a port of the RTEMS OS runs on MPARM, and a linux port is well underway.
last . updated: 03.02.2005
M P A R M . s t a t u s
processor . models
SWARM (ARMv7). Fully functional.
CoWare LISATek cores. Support for the SystemC LISATek interface is underway.
OCP traffic generator. This traffic generator is capable of replicating, emulating or generating traffic by means of detailed programs, with support for branches, internal registers and I/O checking.
SimIt-ARM (StrongARM). Working OK. Low-level MMU/interrupt features required for a full-blown OS port are missing.
PowerPC 750. Working OK. Currently non-reentrant portions of code prevent multiple instantiation, but this will be fixed soon. Low-level MMU/interrupt features required for a full-blown OS port are missing.
MIPS R3000. Porting is almost complete.

interconnect . models
AMBA AHB. Various models are available, written both in pure SystemC and (under STMicroelectronics NDA) developed with the OCCN libraries. AHB to AHB bridges are available. Multilayer (crossbar) components are available.
STBus (under STMicroelectronics NDA) interconnect. Type 3 nodes are supported, in various topologies.
xpipes NoC. This NoC was developed in-house. Porting is almost done, with final debugging and statistics collection going on.

device . models
Scratchpad memories (as cache replacements, as local buffers and as point-to-point interprocessor queues).
Snoop devices (to provide cacheability in multiprocessor shared-memory environments).
Synchronization devices (semaphores, inter-processor interrupt devices).
DMA controllers.
"Smart memories" (memories with built-in DMA engines).
Frequency scaling devices (to provide runtime frequency and voltage scaling; includes dual-frequency FIFOs to attach components to each other).
FFT engine.

software . ports
RTEMS is working on MPARM (with the SWARM ISS).
linux runs on MPARM (with the SWARM ISS), but currently only as a uniprocessor kernel independently replicated on every processor. Drivers for DMA devices etc. are still missing.
last . updated: 03.02.2005
h e l p . w a n t e d
benchmark . development
Development and porting of benchmarks from multiple domains (multimedia, networking, data encryption), to increase the available SoC test suite.

module . synthesizability
Re-coding of many available behavioral SystemC modules to make them available for synthesis, including FPGA mapping and possibly test chips.

NoC . exploration
Exploration of NoC performance when varying key architectural features, including flow control policies, routing policies, buffering resources, virtual channels, quality-of-service provision.
last . updated: 05.02.2005
M P A R M . t h e s e s
Sergio . Foresta
Progetto di una architettura Very Long Instruction Word per applicazioni a basso consumo di potenza (Design of a Very Long Instruction Word Architecture for Low Power Applications)

last . updated: 27.08.2007
M P A R M . p r o j e c t s
ram . controller
Development of a memory controller hosting a DMA engine and taking care of moving data to and from an external DRAM device.

fpga . mapping
Mapping on FPGA of as many components of MPARM as possible, to get faster simulation speed and more accurate area comparisons.

communication . paradigms
Study of the scalability of different communication paradigms (ranging from shared-memory with cache coherency to message passing) under different stress patterns.

benchmark . development
Development and porting of benchmarks from multiple domains (multimedia, networking, data encryption), to increase the available SoC test suite.

power . models
Power models of as many components of MPARM as possible, with particular emphasis on interconnect fabrics (including bridges, crossbars and NoCs).

frequency . scaling
Maximum flexibility in instantiation of components at different frequencies, including runtime (OS- or HW-controlled) programmable frequency scaling, synchronization FIFOs, voltage scaling, and related power modeling.

thermal . models
Simulation-linked models to predict the heating of a die as a function of switching activity in chip hotspots.

OCP . framework
Deployment of OCP at device boundaries, to get a completely plug-and-play architecture.

topology . instantiation
Specification and runtime parsing of a file in XML format to specify the configuration parameters of a whole SoC.
last . updated: 05.02.2005
M P A R M . c o o p e r a t e s
academic . cooperations
Stanford University
Université Paris 6
Università di Roma La Sapienza
Università di Verona
Politecnico di Torino
Università di Urbino
Università di Cagliari
École Polytechnique Fédérale de Lausanne
Universidad Complutense de Madrid
Universidad Politécnica de Madrid
Aachen Technical University
Technical University of Denmark
Penn State University
Swiss Federal Institute of Technology (ETH) Zurich
Linköpings Universitet

industrial . cooperations
STMicroelectronics (CMG and AST)
last . updated: 14.02.2005
M P A R M . d o w n l o a d s
what . available
MPARM distribution to third parties is decided on a case by case basis. If you have a project where you believe MPARM could be useful, you or your advisor should contact Prof. Luca Benini with a brief description of the project.
On this site, following the link below, you'll have access to the support material of MPARM: a SystemC package, a x86/ARM cross-compiler, the seyon tool for simulation monitoring, and some minimal documentation.

files . here
Tools and some documentation
last . updated: 03.06.2004
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