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short . summary
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Federico Angiolini was born in Bologna, Italy, on July 21st, 1978. He received the M.S. degree (summa cum laude) in Electronical Engineering (specialization in Computer Architecture) from the University of Bologna in 2003. Since may 2003 he is working with the University of Bologna on the topics of multiprocessor system simulation, networks on chip, memory hierarchies and fault-tolerant nanoscale PLA devices. Since january 2005, he is a Ph.D. student at the same University.
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last . updated: 28.02.2006
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my . interests
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Federico Angiolini's research is mostly in the field of embedded systems. He is currently involved in cycle-accurate simulation infrastructures for multiprocessor embedded systems, and in the design and comparative analysis of interconnects for such environments, ranging from traditional shared buses to innovative packet-switching Network-on-Chip (NoC) subsystems. The aim of his research is the exploration of the design space to identify optimal architectural tradeoffs among speed, area and power.
Additionally, he is working on the topic of memory hierarchies, with emphasis on the usage of ScratchPad Memories (SPMs). Within this context, he has explored both static approaches, based upon dedicated hardware synthesis, and purely software-oriented solutions.
Recently, he got interested in nanoscale manufacturing of devices, and is at work on fault tolerance for nano-PLAs.
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useful . stuff
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my . photo (tiff . eps)
university . logo (official . bw . big)
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last . updated: 12.10.2005
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m y . c u r r i c u l u m
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last . updated: 14.03.2006
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t e a c h i n g . a c t i v i t y
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last . updated: 08.10.2005
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m y . p u b l i c a t i o n s
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master . thesis
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F. Angiolini, Algoritmi per il partizionamento automatico di memorie per sistemi a processore integrati a basso consumo
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conference . papers
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F. Angiolini, L. Benini, A. Caprara, Polynomial-Time Algorithm for On-Chip Scratchpad Memory Partitioning, Proceedings of the 2003 ACM International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), San José (CA), USA, Oct 30 - Nov 1, 2003, pp. 318-326 (presentation)
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M. Loghi, F. Angiolini, D. Bertozzi, L. Benini, R. Zafalon, Analyzing On-Chip Communication in a MPSoC Environment, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition 2004, Paris, France, Feb 16-20, 2004, pp. 752-757 (presentation)
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F. Angiolini, F. Menichelli, A. Ferrero, L. Benini, M. Olivieri, A Post-Compiler Approach to Scratchpad Mapping of Code, Proceedings of the 2004 ACM International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), Washington (DC), USA, Sep 22-25, 2004, pp. 259-267 (presentation)
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M. Ruggiero, F. Angiolini, F. Poletti, D. Bertozzi, L. Benini, R. Zafalon, Scalability Analysis of Evolving SoC Interconnect Protocols, Proceedings of the 2004 International Symposium on System-on-Chip, Tampere, Finland, Nov 16-18, 2004, pp. 169-172 (poster)
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S. Mahadevan, F. Angiolini, M. Storgaard, R. G. Olsen, J. Sparsø, J. Madsen, A Network Traffic Generator Model for Fast Network-on-Chip Simulation, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition 2005, Munich, Germany, Mar 7-11, 2005, pp. 780-785 (presentation)
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S. Stergiou, F. Angiolini, S. Carta, L. Raffo, D. Bertozzi, G. De Micheli, xpipes Lite: A Synthesis Oriented Design Flow For Networks on Chips, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition 2005, Munich, Germany, Mar 7-11, 2005, pp. 1188-1193 (presentation)
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A. Pullini, F. Angiolini, D. Bertozzi, L. Benini, Fault Tolerance Overhead in Network-on-Chip Flow Control Schemes, Proceedings of 18th Annual Symposium on Integrated Circuits and System Design (SBCCI) 2005, Florianópolis, Brazil, Sep 4-7, 2005, pp. 224-229 (presentation)
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F. Angiolini, P. Meloni, D. Bertozzi, L. Benini, S. Carta, L. Raffo, Networks on Chips: A Synthesis Perspective, Proceedings of the Parallel Computing (ParCo) Conference 2005, Málaga, Spain, Sep 13-16, 2005 (presentation)
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S. Srinivasan, F. Angiolini, M. Ruggiero, N. Vijaykrishnan, L. Benini, Simultaneous Memory and Bus Partitioning for SoC Architectures, Proceedings of the IEEE International SOC Conference (SOCC) 2005, Washington (DC), USA, Sep 25-28, 2005, pp. 125-128 (presentation)
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F. Angiolini, S. Mahadevan, J. Madsen, L. Benini, J. Sparsø, Realistically Rendering SoC Traffic Patterns with Interrupt Awareness, Proceedings of the IFIP VLSI-SOC Conference 2005, Perth (WA), Australia, Oct 17-19, 2005, pp. 211-216 (presentation)
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F. Angiolini, P. Meloni, S. Carta, L. Benini, L. Raffo, Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition 2006, Munich, Germany, Mar 6-10, 2006, pp. 124-129 (presentation)
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F. Angiolini, J. Ceng, R. Leupers, F. Ferrari, C. Ferri, L. Benini, An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition 2006, Munich, Germany, Mar 6-10, 2006, pp. 1145-1150 (presentation)
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P. Meloni, S. Carta, R. Argiolas, L. Raffo, F. Angiolini, Area and Power Modeling Methodologies for Networks-on-Chip, Proceedings of the Nano-Net Conference 2006, Lausanne, Switzerland, Sep 14-16, 2006 (presentation)
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F. Angiolini, D. Atienza, S. Murali, L. Benini, G. De Micheli, Reliability Support for On-Chip Memories Using Networks-on-Chip, Proceedings of the International Conference on Computer Design (ICCD) 2006, San José (CA), USA, Oct 1-4, 2006 (presentation)
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S. Murali, P. Meloni, F. Angiolini, D. Atienza, S. Carta, L. Benini, G. De Micheli, L. Raffo, Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips, Proceedings of the IFIP VLSI-SOC Conference 2006, Nice, France, Oct 16-18, 2006, pp. 158-163 (presentation)
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S. Murali, P. Meloni, F. Angiolini, D. Atienza, S. Carta, L. Benini, G. De Micheli, L. Raffo, Designing Application-Specific Networks on Chips with Floorplan Information, Proceedings of the International Conference on Computer Aided Design (ICCAD) 2006, San José (CA), USA, Nov 5-9, 2006, pp. 355-362 (presentation)
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S. Murali, R. Tamhankar, F. Angiolini, A. Pullini, D. Atienza, L. Benini, G. De Micheli, Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips, Proceedings of the 2006 International Symposium on System-on-Chip, Tampere, Finland, Nov 13-16, 2006, pp. 27-30 (presentation)
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F. Angiolini, M. H. Ben Jamaa, D. Atienza, L. Benini, G. De Micheli, Improving the Fault Tolerance of Nanometric PLA Designs, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition 2007, Nice, France, Apr 16-20, 2007, pp. 570-575 (presentation)
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A. Pullini, F. Angiolini, P. Meloni, D. Atienza, S. Murali, L. Raffo, G. De Micheli, L. Benini, NoC Design and Implementation in 65nm Technology, Proceedings of the 1st ACM/IEEE International Symposium on Networks-on-Chip, Princeton (NJ), USA, May 7-9, 2007, pp. 273-282 (presentation)
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I. Loi, F. Angiolini, L. Benini, Supporting vertical links for 3D networks on chip: toward an automated design and analysis flow, Proceedings of the Nano-Net Conference 2007, Catania, Italy, Sep 24-26, 2007 (presentation)
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I. Loi, F. Angiolini, L. Benini, Developing Mesochronous Synchronizers to Enable 3D NoCs, to be published in the Design, Automation and Test in Europe Conference and Exhibition 2008 (presentation)
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journal . papers
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F. Angiolini, L. Benini, A. Caprara, An Efficient Profile-Based Algorithm for Scratchpad Memory Partitioning, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Nov 2005, Vol. 24 Issue 11, pp. 1660-1676
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F. Angiolini, P. Meloni, S. Carta, L. Raffo, L. Benini, A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Mar 2007, Vol. 26 Issue 3, pp. 421-434
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R. Tamhankar, S. Murali, S. Stergiou, A. Pullini, F. Angiolini, L. Benini, G. De Micheli, Timing Error Tolerant Network-on-Chip Design Methodology, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jul 2007, Vol. 26 Issue 7, pp. 1297-1310
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P. Meloni, I. Loi, F. Angiolini, S. Carta, M. Barbaro, L. Raffo, L. Benini, Area and Power Modeling for Networks-on-Chip with Layout Awareness, VLSI Design, Vol. 2007, Article ID 50285, 12 pages
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A. Pullini, F. Angiolini, S. Murali, D. Atienza, G. De Micheli, L. Benini, Bringing NoCs to 65nm, IEEE Micro, Sep-Oct 2007, Vol. 27 Issue 5, pp. 75-85
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S. Mahadevan, F. Angiolini, J. Sparsø, L. Benini, J. Madsen, A Reactive and Cycle-True IP Emulator for MPSoC Exploration, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jan 2008, Vol. 27 Issue 1, pp. 109-122
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D. Atienza, F. Angiolini, S. Murali, A. Pullini, L. Benini, G. De Micheli, Network-On-Chip Design and Synthesis Outlook, to be published in Elsevier Integration, the VLSI Journal
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posters . presentations
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F. Angiolini, D. Bertozzi, L. Benini, S. Murali, S. Stergiou, G. De Micheli, P. Meloni, S. Carta, L. Raffo, The SUNMAP/xpipes NoC Synthesis Flow, University Booth at the Design, Automation and Test in Europe Conference and Exhibition 2005, Munich, Germany, Mar 7-11, 2005 (associated flyer, associated presentation)
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S. Murali, D. Atienza, G. De Micheli, F. Angiolini, L. Benini, P. Meloni, S. Carta, L. Raffo, SunFloor: Application-Specific Design of Networks-on-Chip, University Booth at the Design, Automation and Test in Europe Conference and Exhibition 2006, Munich, Germany, Mar 6-10, 2006 (associated flyer)
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F. Angiolini, L. Benini, Exploring the Design Space for Networks-on-Chip, Ph.D. Forum at the Design, Automation and Test in Europe Conference and Exhibition 2006, Munich, Germany, Mar 6-10, 2006 (associated flyer)
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F. Angiolini, L. Benini, L. Lerin, D. Bertozzi, Assessing the Behaviour of Adaptive Routing in NoCs through Cycle-Accurate Functional Simulation, NoC Workshop at the Design, Automation and Test in Europe Conference and Exhibition 2006, Munich, Germany, Mar 6-10, 2006
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F. Angiolini, L. Benini, Networks-on-Chip: From Idea to Implementation, Ph.D. Forum at the Design, Automation and Test in Europe Conference and Exhibition 2007, Nice, France, Apr 16-20, 2007
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last . updated: 27.09.2007
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