Dipartimento di Elettronica, Informatica e Sistemistica


Micrel Lab @ DEIS - Dipartimento di Elettronica, Informatica e Sistemistica - Facoltà di Ingegneria - Università di Bologna Viale Risorgimento 2,
40136 Bologna - ITALY

+39 051 2093782

+39 051 2093073
+39 051 2093785


The above address is meant to avoid spam spiders
turn the (#) into a @ and the (*) into a .

Prof. Luca Benini



Luca Benini is an Full Professor at the University of Bologna. He also holds a visiting faculty position at the Ecole Polytecnique Federale de Lausanne (EPFL). He received a Ph.D. degree in electrical engineering from Stanford University in 1997. Dr. Benini's research interests are in the design of systems for ambient intelligence, from multi-processor systems-on-chip/networks on chip to energy-efficient smart sensors and sensor networks.From there his research interest have spread into the field of biochips for the recognition of biological molecules, and into bioinformatics for the elaboration of the resulting information and further into more advanced algorithms for in silico biology. He has published more than 300 papers in peer-reviewed international journals and conferences, three books, several book chapters and two patents. He has been program chair and vice-chair of Design Automation and Test in Europe Conference. He has been a Member of the 2003 MEDEA+ EDA roadmap committee 2003. He is a member of the IST Embedded System Technology Platform Initiative (ARTEMIS): working group on Design Methodologies, a Member of the Strategic Management Board of the ARTIST2 Network of excellence on Embedded Syste and a Member of the Advisory group on Computing Systems of the IST Embedded Systems Unit.
He has been member of the technical program committee and organizing committee of several technical conferences, including the Design Automation Conference, International Symposium on Low Power Design, the Symposium on Hardware-Software Codesign. He is Associate Editor of the IEEE Transactions on Computer-Aided Design of Circuits and Systems and of the ACM Journal on Emerging Technologies in Computing Systems. He is a Fellow of the IEEE.




Elettronica L-B, Corso di laurea in Ingegneria Informatica.
Affidabilita' e diagnostica, Corso di laurea in Ingegneria Elettronica.
Elettronica Applicata I, Corso di laurea in Ingegneria Elettronica, Informatica, Telecomunicazioni.
Elettronica Applicata II, Corso di laurea in Ingegneria Elettronica, Informatica, Telecomunicazioni.
Metodologie di Progettazione Hardware-Software, Corso di laurea specialistica in Ingegneria Elettronica (a scelta, per Informatica, Telecomunicazioni).
Biosensori, Corso di Laurea in Scienze Matematiche, Fisiche e Naturali




General Web Site: Micrel Group @ DEIS @ ING @ UNIBO

System and Network on Chip [ info | MPARM ]

Wireless Sensor Network and Ambient Intelligence [web site | research | videos]

Bioinformatics and Biosensors [info]



Some of the people I work with

Elisabetta Farella
Christine Nardini

Ph.D. Students

XIX ciclo
Davide Brunelli
Claudio Stagni 
Francesco Poletti

XX ciclo
Martino Ruggiero
Federico Angiolini 
XXI ciclo
Piero Zappi
Giacomo Paci

Research fellows
Omar Cafini
Andrea Marongiu
Luciano Ruggiero
Paolo Lombardo
Michele Magno

Research Associates 
Andrea Acquaviva also Assistant Professor at the University of Urbino
Davide Bertozzi also Assistant
Professor at the University of Ferrara
Augusto Pieracci
Research Consultant
Carlotta Guiducci also
post-doc at Ecole Normale Paris

Mirko Loghi also
PhD student at the University of Verona

Elisa Ficarra also
Post-Doc at the Politecnico of Torino

Daniele Masotti also
PhD student at the Politecnico of Torino

Paolo Meloni also
PhD with Univ. of Cagliari

Igor Loi also
Research Associate with Univ. of Cagliari

Simone Medardoni also
PhD with Univ.
of Ferrara
Antonio Pullini also
Research fellow at the Politecnico of Torino

Salvatore Carta also
Research fellow at University of Cagliari

David Atienza also assistant professor at Complutense University of Madrid and Post-Doc at EPFL - Losanne





Micrel Group Full Publications List 2006 | 2005 e 2004 | 2003 | 2002 | 2001 | Cerca

Most frequently referred papers

[1] L. Benini, P. Siegel, G. De Micheli, "Saving power by synthesizing gated clocks for sequential circuits," IEEE Design & Test of Computers, vol. 11, no. 4, pp. 32-40, Winter 1994.
This paper posed the theoretical and algorithmic foundations for the automatic instantiation of gated clocks. Clock gating has become one of the cornerstones of power optimization, and this paper was among the first to demonstrate that the extraction of clock gating conditions and the instantiation of clock-gating circuits can be automated. The techniques proposed in this paper have found applications in many commercial EDA tools for power optimization. An enhancement of this work have been successfully patented: US Patent. N. 6,704,678, L. Benini, J. Sproch, B. Wurth "Apparatus and method for improved precomputation to minimize power dissipation of integrated circuits", 2004

[2] L. Benini, A. Bogliolo, G. Paleologo, G. De Micheli, "Policy Optimization for Dynamic Power Management," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 6, pp. 813-833, June 1999.
This paper introduced a theoretical framework for the analysis and the optimization of power-management policies based on shutdown. The problem of finding an optimal shutdown policy is cast as a stochastic optimization problem and it is optimally solved in polynomial time using the theory of Markov decision processes. The work presented in this paper has been at the basis of many later contributions in the area of power management. Policy optimization techniques are now commonly used in industry.

[3] L. Benini, G. De Micheli, "Networks on chip: a new SoC paradigm", IEEE Computer, vol. 35, no. 1, Jan. 2002.
This work presented a new approach to the design of on-chip interconnects. It outlined the need for a paradigm shift from bus-based solution to scalable and compositional fabrics. It also provided a conceptual framework for the development of new design flows and tools for large-scale, communication-dominated integrated systems. This paper is commonly referenced by researchers in the area, and it contributed to the development of interconnect architectures that are finding wide adoption in the semiconductor industry

Other Selected publications

Computer-aided design for low-power

1. L. Benini, G. De Micheli, E. Macii, M. Poncino, R. Scarsi, ``A Multi-level Engine for Fast Power Simulation of Realistic Input Streams,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 4, pp. 459--472, April 2000. This paper tackles the problem of accelerating power-estimation at the gate level without compromising activity, exploiting multi-level simulation.
2. A. Acquaviva, L. Benini, B. Riccò, ``
Software-controlled processor speed setting for low-power streaming multimedia,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 11, pp. 1283-1292, Nov. 2001. This paper presents an original application-directed technique for controlling the speed of variable-frequency processors for multi-media decoding.
3. L. Benini, D. Bruni, A. Macii, E. Macii, M. Poncino, "
Discharge Current Steering for Battery Lifetime Optimization", IEEE Transactions on Computers, Vol. 52, No. 8, pp. 985-995, August 2003, IEEE Press, Piscataway, NJ, USA. This is one of the first approaches to battery-aware power management of alectronic systems. New policies are presented for enhancing battery lifetime directly, as opposed to traditional approaches targeting average power minimization
4. F. Menichelli, L. Benini, M. Olivieri, "
A Class of Code Compression Schemes for Reducing Power Consumption in Embedded Microprocessor Systems", IEEE Transaction on Computers, 53(4): 467-482, 2004. This paper presents novel code compression scheme that significantly reduced instruction memory power consumption for embedded processors.
5. Bogliolo, A.; Benini, L.; Lattanzi, E.; De Micheli, G.; "
Specification and analysis of power-managed systems" Proceedings of the IEEE , 92(8):1308-1346, Aug. 2004. This paper exploits the theory of generalized-semi-Markov decision processes to describe, analyze and optimize a wide variety of power-manageable systems (from variable-voltage processors to sensor networks)

Logic synthesis and memory architecture synthesis

1. L. Benini, P. Vuillod, G. De Micheli, "Iterative re-mapping for logic circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. vol. 17, no. 10, pp. 948-964, Oct. 1998. This paper presented a very general Boolean matching technique to find library gates that match a sub-netlist in a given combinational logic circuit. An efficient BDD-based implementation is also described.
2. L. Benini, G. De Micheli, E. Macii, M. Poncino, "
Telescopic units: a new paradigm for performance optimization of VLSI designs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 3, pp. 220-232, March 1998. This paper presents a technique for automating the creation of variable-latency functional units, extending techniques are manually applied in full-custom circuit design.
3. F. Angiolini, L. Benini, A. Caparra, "
An efficient profile-based algorithm for scratchpad memory partitioning" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, no. 11, pp. 1660-1676, Nov. 2005. This paper describes a computationally efficient technique for automatic synthesis of a partitioned (multi-bank) scratchpad memory tuned for a given access profile.

System-on-chip and Network on chip: modeling, design and synthesis.

1. Benini, D. Bertozzi, D. Bruni, N. Drago, F. Fummi, M. Poncino, "SystemC Cosimulation and Emulation of Multiprocessor SoC Designs", IEEE Computer, Volume: 36 Issue: 4, April 2003 Page(s): 53 -59. This paper presents a technique for building a simulation platform for multi-processors architectures in a modular fashion, using existing simulation models. This work pioneered the now well-known concept of "virtual platform"
2. A. Jalabert, S. Murali; R. Tamhankar, S. Stergiou, D. Bertozzi, L. Benini, G. De Micheli, "
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip", IEEE Transactions on Parallel and Distributed Systems, vol. 16, no. 2, pp. 113-129, Feb 2005. This paper describes the first NoC synthesis flow from high-level specification of a communication graph to synthesizable RTL.
3. L. Benini, D. Bertozzi, "
Network-on-chip architectures and design methods," IEE Proceedings - Computers and Digital Techniques, vol. 152, no. 2, pp. 261-272, Mar 2005. This paper surveys network on-chip architectures and NoC design issues, and describes the architecture of the Xpipes nerwork on-chip.

DNA sensors, Biochips and DNA microarray signal processign and data mining

1. C. Guiducci, C. Stagni, G. Zuccheri, A. Bogliolo, L. Benini, B. Samorì. B. Riccò, "DNA Detection by Integrable Electronics", Biosensors and Bioelectronics, 19(1):781-787, 2004. This paper presents a label-free capacitive sensor for detecting DNA hybridization. This sensor is well suited to single-chip integration.
2. S. Yoon, C. Nardini, L. Benini, G. De Micheli, "Discovering Coherent Biclusters from Gene Expression Data Using Zero-suppressed Binary Decision Diagrams," IEEE/ACM Transactions on Computational Biology and Bioinformatics vol. 2, no. 4, pp. 339-354, Oct.-Dec. 2005. This paper presents a novel technique for computing all high-affinity bi-clusters in a data matrix, using symbolic manipulation techniques.
3. E. Ficarra, D. Masotti, E. Macii, L. Benini, G. Zuccheri, B. Samori, "Automatic intrinsic DNA curvature computation from AFM images", IEEE Transactions on Biomedical Engineering, Vol. 52, no. 12, pp. 2074-2086, Dec. 2005. This paper describes the first fully automated technique for dentifying DNA molecules and computing their curvature in atomic force microscope images.
4. C. Stagni Degli Esposti, C. Guiducci. C. Paulus, M. Schiele, M. Augustyniak, G. Zuccheri, B. Samorì, L. Benini, B. Riccò, R. Thewes, "Fully Electronic CMOS DNA Detection Array Based on Capacitance Measurement with On-Chip Analog-to-Digital Conversion", International Solid-State Circuit Conference, 2006. This paper presents the first label-free fully electronic DNA chip based on interface capacitance measurement in CMOS technology.

Ambient intelligence and wireless sensor networks

1. Elisabetta Farella, Davide Brunelli, Luca Benini, Bruno Riccò, Maria Elena Bonfigli, "Pervasive Computing for Interactive Virtual Heritage," IEEE MultiMedia ,vol. 12, no. 3, pp. 46-58, July-September, 2005. A platform for interactive virtual heritage applications integrates a high-end virtual reality system with wireless, connected wearable computers, facilitating and enhancing user navigation, visualization control, and peer-to-peer information exchange.
2. Elisabetta Farella, Augusto Pieracci, Davide Brunelli, Luca Benini, Bruno Riccò, Andrea Acquaviva: "Design and Implementation of WiMoCA Node for a Body Area Wireless Sensor Network". IEEE ICW/ICHSN/ICMCS/SENET 2005: 342-347. This paper presents the design and implementation of a wireless sensor node for a Motion Capture system with Accelerometers (WiMoCA). WiMoCA nodes implement a Wireless Body Area Sensor Network (WBASN) for wireless/wearable distributed gesture recognition system.
3. Sama, M.; Pacella, V.; Farella, E.; Benini, L.; Ricco, B., "3dID: a Low-power, Low-cost Hand Motion Capture Device," Design, Automation and Test in Europe, 2006. DATE '06. Proceedings , vol.2, no.pp. 1- 6, 06-10 March 2006. This paper presents a novel low-power, low-cost input glove device design for capturing gestures. It can be used as a stand-alone platform or combined with other wireless sensor nodes in a body area network.
4. Brunelli, D.; Farella, E.; Rocchi, L.; Dozza, M.; Chiari, L.; Benini, L., "Bio-feedback system for rehabilitation based on a wireless body area network," Pervasive Computing and Communications Workshops, 2006. PerCom Workshops 2006. Fourth Annual IEEE International Conference on , vol., no.pp. 5 pp.-, 13-17 March 2006. In this paper we describe BIO-WWS, a bio-feedback system for rehabilitation based on dedicated, wireless, sensor-network architecture. The sensor network is designed to be distributed on the user's body for balance monitoring and correction.
5. Prati, A., Vezzani, R., Benini, L., Farella, E., and Zappi, P. 2005. "An integrated multi-modal sensor network for video surveillance". In Proceedings of the Third ACM international Workshop on Video Surveillance &Amp; Sensor Networks (Hilton, Singapore, November 11 - 11, 2005). VSSN '05. ACM Press, New York, NY, 95-102. To enhance video surveillance systems, multi-modal sensor integration can be a successful strategy. In this work, a computer vision system able to detect and track people from multiple cameras is integrated with a wireless sensor network mounting PIR (Passive InfraRed) sensors.
6. Clemens Moser, Davide Brunelli, Lothar Thiele, Luca Benini "Lazy Scheduling for Energy Harvesting Sensor Nodes" 5th IFIP Working Conference on Distributed and Parallel Embedded Systems DIPES 2006, Braga, Portugal, October, 2006. Energy harvesting has recently emerged as a viable option to increase the lifetime of sensor nodes. In this field, we have conducted research in order to optimize the energy flow on a sensor node under real-time predictability constraints.



Cooperation, European Projects, National Projects...