Pubblications

Journal-Paper

• P. Meloni, I. Loi, F. Angiolini, S. Carta, M. Barbaro, L. Raffo and L. Benini, "Area and Power Modeling for Networks-on-Chip with Layout Awareness" VLSI Design, March 2007.

Conference-Paper

• I. Loi, F. Angiolini and L. Benini "Supporting vertical links for 3D networks on chip: toward an automated design and analysis flow" Proceedings of the Nano-Net Conference 2007, Catania, Italy, Sep 24-26, 2007
• I.Loi, F.Angiolini and L.Benini "Developing Mesochronous Sychronizer to enable 3D NoCs", Procedings of the Date Conference, 10-14 March 2008, Munich, Germany