Research

Igor Loi received the M.S. degree in electronic engineering from the University of Cagliari, Italy, in 2005. He is currently a Ph.D. student in the Department of electronics and computer science in the University of Bologna, where his research is mostly focused upon three dimensional integrated circuit interconnection, Networks-on-Chip and Nanotecnologies

His research interests concern design and analysis of Three Dimensional Integrated Circuit, with particular emphasis on the On-Chip Inteconnects applied on Three Dimensional Network on Chip.

Other research interests include Multi Processor Sistem on Chip (MPSOC) and System on Chip (SoC) design Flow and analisys, Voltage scaling and Multi threshold voltages Techinque (Backend)

Igor Loi has been academic guest and visiting researcher at Stanford University, California (USA) from Sept 2007 to Jan 2008. During this visit he worked on Fault Tolerance of Through Silicon Vias and he formulated a promising approach to increase the Yield on three dimensionanal Integrated circuit.