Publications


  1. M. Damiani, P. Olivo, M. Favalli, B. Ricco'
    Aliasing Errors in Signature Analysis Testing of Integrated Circuits
    IEEE International Conference on Computer Design (ICCD)
    pp. 458-461, Rye Brook (N.Y), Oct. , 1988.


  2. M. Damiani, P. Olivo, M. Favalli, B. Ricco'
    An Analytical Model for the Aliasing Probability in Signature Analysis Testing
    IEEE Transactions on Computer Aided Design
    vol. CAD-8, pp. 1133-1144, Nov., 1989.


  3. S. Ercolani, M. Favalli, M. Damiani, P. Olivo, B. Ricco'
    Improved Testability Evaluations in Combinational Logic Networks
    IEEE International Conference on Computer Design (ICCD)
    pp. 352-355, Cambridge (Mass.), Oct., 1989.


  4. M. Favalli, P. Olivo, M. Damiani, B. Ricco'
    CMOS Design for Improved IC Testability
    IEEE International Test Conference (ITC)
    p. 934, Washington (USA), Aug., 1989.


  5. S. Ercolani, M. Favalli, M. Damiani, P. Olivo, B. Ricco'
    Estimate of Signal Probability in Combinational Logic Network
    IEEE European Test Conference (ETC)
    pp. 132-138, Paris (France), Apr., 1989.


  6. M. Damiani, P. Olivo, M. Favalli, S. Ercolani, B. Ricco'
    Aliasing in Signature Analysis Testing with Multiple-Input Shift-Registers
    IEEE European Test Conference (ETC)
    pp. 346-353, Paris (France), Apr., 1989.


  7. M. Favalli, P. Olivo, M. Damiani, B. Ricco'
    Novel Design for Testability Schemes for CMOS ICs
    IEEE Journal of Solid State Circuits
    vol. SC-25, pp. 1239-1246, Oct., 1990.


  8. M. Favalli, P. Olivo, B. Ricco'
    A Circuit for the Detection of Delay Faults in CMOS ICs
    IEEE European Workshop on Design for Testability
    Segovia (Spain), Jun., 1990.


  9. M. Favalli, P. Olivo, B. Ricco'
    Progettazione Orientata al Collaudo di Circuiti Integrati Digitali
    Alta Frequenza - Rivista di Elettronica
    vol. II, pp. 55-64, Apr., 1990.


  10. M. Damiani, P. Olivo, M. Favalli, S. Ercolani, B. Ricco'
    Aliasing in Signature Analysis Testing with Multiple-Input Shift-Registers
    IEEE Transactions on Computer Aided Design
    vol. CAD-9, pp. 1344-1353, Dec., 1990.


  11. M. Favalli, P. Olivo, B. Ricco'
    A Novel Critical Path Heuristic for Fast Fault Grading
    IEEE Transactions on Computer Aided Design
    vol. CAD-10, pp. 544-548, Apr., 1991.


  12. M. Favalli, S. Ercolani, M. Dalpasso, P. Olivo, B. Ricco'
    Weighted Pseudorandom Generation for Built-In Self-Test
    IEEE COMPEURO
    Bologna (Italy), pp. 572-574, May., 1991.


  13. M. Ambanelli, M. Favalli, M. Dalpasso, P. Olivo, B. Ricco'
    Fault Simulation of Multiple Faults in PLAs
    IEEE COMPEURO
    Bologna (Italy), pp. 229-232, May., 1991.


  14. B. Ricco', M. Favalli, P. Olivo
    Comprehensive Fault Modeling and Simulation in CMOS ICs
    IEEE COMPEURO
    Bologna (Italy), pp. 778-785, May., 1991.


  15. M. Dalpasso, M. Favalli, P. Olivo, B. Ricco'
    Switch-Level Fault Simulation by Critical Path Tracing
    IEEE European Test Conference (ETC)
    Munich (Germany), pp. 181-190, Apr., 1991.


  16. M. Favalli, P. Olivo, B. Ricco'
    A Probabilistic Fault Model for Analog Faults in CMOS Circuits
    European Design Automation Conference (EDAC)
    Amsterdam (The Nederlands), pp. 85-88, Feb., 1991.


  17. M. Ambanelli, M. Favalli, P. Olivo, B. Ricco'
    Detection of PLA Multiple Crosspoint Faults
    European Design Automation Conference (EDAC)
    Amsterdam (The Nederlands), pp. 80-84, Feb., 1991.


  18. B. Ricco', M. Favalli, L. Selmi
    Logiche di Tipo BiCMOS
    Alta Frequenza - Rivista di Elettronica
    vol. III, pp. 25-36, Jan., 1991.


  19. M. Favalli, P. Olivo, F. Somenzi, B. Ricco'
    Fault Simulation for General FCMOS ICs
    Journal of Electronic Testing, Theory and Applications
    vol. 2, pp. 181-190, Jun., 1991.


  20. M. Favalli, P. Olivo, M. Damiani, B. Ricco'
    Fault Simulation of Unconventional Faults in CMOS Circuits
    IEEE Transactions on Computer Aided Design
    vol. CAD-10, pp. 677-682, May., 1991.


  21. S. Ercolani, M. Favalli, M. Damiani, P. Olivo, B. Ricco'
    Testability Measures in Pseudorandom Testing
    IEEE Transactions on Computer Aided Design
    vol. CAD-11, pp. 794-800, Jun., 1992.


  22. M. Favalli, M. Dalpasso, P. Olivo, B. Ricco'
    Analysis of Steady State Detection of Resistive Bridging Faults in BiCMOS Digital Circuits
    IEEE International Test Conference (ITC)
    Baltimore (Maryland), pp. 466-475, Sep., 1992.


  23. M. Dalpasso, M. Favalli, P. Olivo, B. Ricco'
    Parametric Bridging Fault Characterization for the Fault Simulation of Library-Based ICs
    IEEE International Test Conference (ITC)
    Baltimore (Maryland), pp. 486-495, Sep., 1992.


  24. C. Metra, M. Favalli, P. Olivo, B. Ricco'
    CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults
    IEEE International Test Conference (ITC)
    Baltimore (Maryland), pp. 948-957, Sep., 1992.


  25. M. Lanzoni, M. Favalli, P. Olivo, B. Ricco'
    An Experimental Study of Testing Techniques for Bridging Faults in CMOS ICs
    IEEE European Worskhop on Design for Testability
    Brugge (Belgium), Jun., 1992.


  26. C. Metra, M. Favalli, P. Olivo, B. Ricco'
    CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults
    IEEE European Worskhop on Design for Testability
    Brugge (Belgium), Jun., 1992.


  27. M. Favalli, P. Olivo, B. Ricco'
    Dynamic Effects in the Detection of Bridging Faults in CMOS ICs
    IEEE European Worskhop on Design for Testability
    Brugge (Belgium), Jun. , 1992.


  28. M. Favalli, M. Dalpasso
    Simulazione di guasti in circuiti integrati digitali
    Alta Frequenza - Rivista di Elettronica
    vol. IV, pp. 13-22, Gen. , 1992.


  29. M. Favalli, P. Olivo, B. Ricco'
    A Probabilistic Fault Model for "Analog" Faults in Digital CMOS Circuits
    IEEE Transactions on Computer Aided Design
    vol. CAD-11, pp. 1459-1462, Nov. , 1992.


  30. M. Favalli, P. Olivo, B. Ricco'
    Dynamic Effects in the Detection of Bridging Faults in CMOS ICs
    Journal of Electronic Testing, Theory and Applications
    vol. 3, pp. 197-205, Aug. , 1992.


  31. M. Lanzoni, M. Favalli, P. Olivo, B. Ricco'
    An Experimental Study of Testing Techniques for Bridging Faults in CMOS ICs
    IEEE Journal of Solid State Circuits
    vol. 28, pp. 686-690, Jun., 1993.


  32. C. Metra, M. Favalli, P. Olivo, B. Ricco'
    A Highly Testable 1-out-of-3 CMOS Checher
    IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
    Venezia (Italy), pp. 279-286, Oct., 1993.


  33. C. Metra, M. Favalli, P. Olivo, B. Ricco'
    Design Rules for CMOS Self-Checking Circuits with Parametric faults in the Functional Block
    IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
    Venezia (Italy), pp. 271-278, Oct., 1993.


  34. M. Favalli, M. Dalpasso, P. Olivo, B. Ricco'
    Analysis of Dynamic Effects of Resistive Bridging Faults in CMOS and BiCMOS Digital ICs
    IEEE International Test Conference (ITC)
    Baltimore (Maryland), pp. 865-874, Oct., 1993.


  35. C. Metra, M. Favalli, P. Olivo, B. Ricco'
    Testing of Resistive Bridging Faults in CMOS Flip-Flop
    IEEE European Test Conference (ETC)
    Rotterdam (The Netherlands), pp. 530-531, Apr., 1993.


  36. M. Dalpasso, M. Favalli, P. Olivo, B. Ricco'
    Influence of IC Synthesis on the Random Pattern Testability of Parametric Bridging Faults
    IEEE European Test Conference (ETC)
    Rotterdam (The Netherlands), pp. 398-407, Apr., 1993.


  37. M. Lanzoni, M. Favalli, P. Olivo, B. Ricco'
    An Implementation of CMOS Design For Testability Techniques for non Stuck-at faults
    International Conference on Microelectronics Test Structures (ICMTS)
    Sitges (Spain), pp. 95-99, Mar., 1993.


  38. M. Favalli, P. Olivo, B. Ricco'
    Testability Measures Combining Probabilistic and Sampling Techniques
    IEEE European Design Automation Conference (EDAC)
    Paris (France), pp. 425-431, Feb., 1993.


  39. L. Benini, M. Favalli, P. Olivo, B. Ricco'
    A Novel Approach to Cost-Effective Estimate of Power in CMOS ICs
    IEEE European Design Automation Conference (EDAC)
    Paris (France), pp. 354-360, Feb., 1993.


  40. M. Favalli, M. Dalpasso, P. Olivo, B. Ricco'
    Analysis of Resistive Bridging Fault Detection in BiCMOS Digital ICs
    IEEE Transactions on VLSI Systems
    vol. 1, pp. 342-355, Sep., 1993.


  41. M. Dalpasso, M. Favalli, P. Olivo, B. Ricco'
    Fault Simulation of Parametric Bridging Faults in CMOS ICs
    IEEE Transactions on Computer Aided Design
    vol. CAD-12, pp. 1403-1410, Sep., 1993.


  42. C. Metra, M. Favalli, B. Ricco'
    Novel 1-out-of-n CMOS checker
    IEE Electronics Letters
    vol. 30, pp. 1398-1400, Aug., 1994.


  43. C. Metra, M. Favalli, P. Olivo, B. Ricco'
    A Novel Berger Code Checker
    IEEE Design For Testability Workshop
    Montreal (Canada), p. 133, 1994.


  44. C. Metra, M. Favalli, B. Ricco'
    Highly Testable and Compact 1-out-of-n CMOS Checkers
    International Workshop on Defect and Fault Tolerance in VLSI Systems
    Montreal (Canada), pp. 142-150, Oct., 1994.


  45. C. Metra, M. Favalli, B. Ricco'
    CMOS Self Checking Circuits with Faulty Sequential Functional Blocks
    International Workshop on Defect and Fault Tolerance in VLSI Systems
    Montreal (Canada), pp. 133-141, Oct., 1994.


  46. L. Benini, M. Favalli, B. Ricco'
    Analysis of hazard contribution to power dissipation in CMOS IC's
    IEEE International Workshop on Low Power Design
    pp. 27-32, May., 1994.


  47. M. Favalli, M. Dalpasso, P. Olivo, B. Ricco'
    Modeling of Broken Connections Faults in CMOS ICs
    IEEE European Design and Test Conference (ED&TC)
    Paris (France), pp. 159-164, Mar., 1994.


  48. C. Metra, M. Favalli, B. Ricco'
    Design of CMOS self-checking sequential circuits with improved detectability of bridging faults
    IEE Electronics Letters
    vol. 30 No.23, pp. 1934-1936, Nov., 1994.


  49. M. Dalpasso, M. Favalli, P. Olivo, J. P. Teixeira
    Realistic Testability Estimates for CMOS IC's
    IEE Electronics Letters
    vol. 30 No.19, p. 1593-1595, Sep., 1994.


  50. C. Metra, M. Favalli, P. Olivo, B. Ricco'
    Design of CMOS Checkers with Improved Testability of Bridging and Transistor Stuck-on Faults
    Journal of Electronic Testing, Theory and Applications
    vol. 6, pp. 7-22, Feb., 1995.


  51. M. Favalli, L. Benini
    Analysis of glitch power dissipation in CMOS IC's
    International Symposium on Low Power Design
    pp. 123-128,, 1995.


  52. M. Favalli, B. Ricco', L. Penza
    A Novel DFT technique for critical bridging faults in CMOS and BiCMOS ICs
    IEEE European Design and Test Conference (ED&TC)
    pp. 568-572, Mar., 1995.


  53. L. Benini, M. Favalli, G. De Micheli
    Generalized Matching: a new approach to concurrent logic optimization and library binding
    International Workshop on Logic Synthesis
    , 1995.


  54. C. Metra, M. Favalli, B. Ricco'
    Novel Berger Code Checker
    IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
    Lafayette (Louisiana), pp. 287-295, Nov., 1995.


  55. M. Favalli, C. Metra
    The Effect of Glitches on Buffer Optimization
    Power And Timing Modeling, Optimization and Simulation Conference (PATMOS)
    Oldenburg (Germany), pp. 202-212, Oct., 1995.


  56. C. Metra, M. Favalli, B. Ricco'
    Glitch Power Dissipation Model
    Power And Timing Modeling, Optimization and Simulation Conference (PATMOS)
    Oldenburg (Germany), pp. 175-189, Oct., 1995.


  57. C. Metra, M. Favalli, B. Ricco'
    Highly Testable 1-out-of-n Dynamic CMOS Checker
    IEEE International On-Line Testing Workshop
    Nice (France), pp. 248-252, Jul., 1995.


  58. M. Dalpasso, M. Favalli, P. Olivo
    Test Pattern Generation for IDDQ: Increasing Test Quality
    IEEE European Design and Test Conference (ED&TC)
    Paris (France), Mar., 1995.


  59. M. Dalpasso, M. Favalli, P. Olivo
    Correlation between IDDQ Testing Quality and Sensor Accuracy
    IEEE European Design and Test Conference (ED&TC)
    Paris (France), Mar., 1995.


  60. M. Favalli, B. Ricco'
    A novel DFT technique for Comprehensive Testing of CMOS buffers
    Alta Frequenza - Rivista di Elettronica
    vol. 7 No.2, pp. 78-80, , 1995.


  61. C. Metra, M. Favalli
    Novel 1-out-of-n Dynamic CMOS Checker
    IEE Electronics Letters
    vol. 31, Nov., 1995.


  62. C. Metra, M. Favalli, B. Ricco'
    Design of TSC CMOS Checkers for any 1-out-of-n Code
    Journal of Microelectronic Systems Integration
    vol. 3 No.2, pp. 81-91, 1995.


  63. M. Favalli, C. Metra
    Sensing circuit on-line detection of delay faults
    IEEE Transactions on VLSI Systems
    vol. 4, n. 1, pp. 130-133, Mar., 1996.

    A sensing circuit for on-line testing of delay faults is presented. It can be used to monitor the outputs of circuits that are either general, or designed to be self-checking with respect to steady state errors. Detailed analyses of the proposed circuit have shown that it is preferable to alternate solutions from the point of view of both the accuracy and the self-testing capability that make it suitable for self-checking applications. Checking architectures for delay faults, making use of the proposed sensing circuit and of standard checkers, are presented.

  64. M. Dalpasso, M. Favalli
    Binary Decision Diagrams (BDDs) for the test pattern generation
    Software for electrical design analysis and design
    95-104, 1996.


  65. L. Benini, A. Bogliolo, M. Favalli, G. De Micheli
    Regression models for behavioral power estimation
    Power, Timing Modeling Optimization and Simulation (PATMOS)
    Bologna (It), pp. 179-187, Sep., 1996.


  66. M. Favalli, L. Benini, G. De Micheli
    Design for testability of gated clock FSMs
    IEEE European Design and Test Conference (ED&TC)
    Paris (Fr), pp. 589-596, Mar., 1996.


  67. M. Favalli, M. Dalpasso, P. Olivo
    Modeling and Simulation of Broken Connections in CMOS ICs
    IEEE Transactions on Computer Aided Design
    vol. 5, n. 7, pp. 808-814, Jul., 1996.


  68. C. Metra, M. Favalli, B. Ricco'
    Compact and Highly Testable Error Indicator for Self-Checking Circuits
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
    Boston (USA), pp. 204-212, Nov., 1996.


  69. C. Metra, M. Favalli, B. Ricco'
    Tree Checkers for Applications with Low Power-Delay Requirements
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
    Boston (MA), p. 213 - 220, Nov.,, 1996.


  70. C. Metra, M. Favalli, B. Ricco'
    Embedded 1-out-of-3 Checkers with On-Line Testing Capability
    IEEE International On-Line Testing Workshop
    St. Jean de Luz (France), p. 136 - 141, Jul., , 1996.


  71. C. Metra, M. Favalli, B. Ricco'
    Embedded Two-Rail Checkers with On-Line Testing Ability
    IEEE VLSI Test Symposium
    Monterey (CA), p. 145 - 150, Apr.,, 1996.


  72. M. Dalpasso, M. Favalli, P. Olivo
    IDDQ test invalidation by break faults
    IEE Electronic Letters
    vol. 32, n. 11, pp. 944-946, , 1996.


  73. M. Favalli, C. Metra
    Low-level Error Recovery Mechanism for Self-Checking Sequential Circuits
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
    Paris (Fr), pp. 234-242, Oct., 1997.

    To match the reliability requirements of small embedded systems, a design methodology is proposed that provides some fault tolerant capabilities to self-checking sequential circuits. By means of simple modifications, such circuits are made fault tolerant with respect to transient, cross-talk and delay faults, while they maintain their self-checking capabilities with respect to permanent faults. The method requires a small area overhead and may also provide some benefit from the yield point of view.

  74. M. Dalpasso, M. Favalli
    A Method for Increasing the IDDQ Testability
    IEEE Transactions on Computer Aided Design
    vol. 16, no. 10, pp. 1186-1188, Oct., 1997.


  75. C. Metra, M. Favalli, B. Ricco'
    On-Line Self-Testing Voting and Detecting Schemes for TMR Systems
    Journal of Microelectronic Systems Integration
    vol. 5, no. 4, pp. 261-273, Dec., 1997.


  76. C. Metra, M. Favalli, P. Olivo, B. Ricco'
    On-Line Detection of Bridging and Delay Faults in Functional Blocks of CMOS Self-Checking Circuits
    IEEE Transactions on Computer Aided Design
    vol. 16, no. 7, pp. 770-776, Jul., 1997.


  77. M. Favalli, C. Metra
    Leakage Power Reduction for Reactive Computation
    Power and Timing, Modeling, Optimization, Simulation (PATMOS)
    Leuven-la-Neuve, pp. 57-66, Sep., 1997.


  78. M. Favalli, M. Dalpasso
    Symbolic handling of bridging fault effects
    Journal of Electronic Testing, Theory and Applications
    vol. 10, n. 3, pp. 271-276, Jun., 1997.


  79. C. Metra, M. Favalli, B. Ricco'
    Compact and Low Power Self-Checking Voting Scheme
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
    Paris (France), pp. 137-145, Oct., 1997.


  80. C. Metra, M. Favalli, B. Ricco'
    On-Line Testing Scheme for Clocks' Faults
    IEEE International Test Conference (ITC)
    Washington D.C. (USA), pp. 587-596, Oct., 1997.


  81. C. Metra, M. Favalli, B. Ricco'
    Self-Checking Detector for Simultaneous On-Line Test of Clock Signals
    IEEE International On-Line Testing Workshop
    Crete (Greece), pp. 79-83, Jul., 1997.


  82. C. Metra, M. Favalli, B. Ricco'
    Novel Single Output 1-out-of-3 Code Checker
    IEEE International On-Line Testing Workshop
    Crete (Greece), pp. 228-232, Jul., 1997.


  83. C. Metra, M. Favalli, B. Ricco'
    Highly Testable and Compact Single Output Comparator
    IEEE VLSI Test Symposium
    Monterey (California), pp. 210-215, Apr., 1997.


  84. C. Metra, M. Favalli, B. Ricco'
    1-out-of-3 Code Checker with Single Output
    IEE Electronics Letters
    vol. 33, p. 1373, 1997.


  85. M. Favalli, C. Metra
    Design of Low-Power CMOS Two-Rail Checkers
    Journal of Microelectronic Systems Integration
    vol. 5, n. 2, pp. 101-110, Jun., 1997.

    This paper presents a novel technique for the reduction of power dissipation in tree-structured two-rail checkers. Such technique exploits the properties of this kind of circuits to perform a level by level power minimization, based on functional or statistic informations on the functional unit outputs. During power minimization the algorithm does not introduce undetectable faults, thus it avoid checker testability degradations. The algorithm has been implemented and power dissipation results are shown for a set of benchmarks.

  86. M. Favalli, C. Metra
    Testing scheme for IC's clock
    IEEE European Design and Test Conference (ED&TC)
    Paris (Fr), pp. 445-449, Mar., 1997.

    This paper proposes a testing scheme to detect abnormal skews between clock signals inside digital synchronous ICs. The scheme is based on a new CMOS sensing circuit whose compactness and testability with respect to a large set of failures make it suitable for both off-line and on-line testing.

  87. C. Metra, M. Favalli, B. Ricco'
    Highly Testable and Compact 1-out-of-n Code Checker with Single Output
    IEEE European Design and Test Conference (ED&TC)
    Paris (France), pp. 981-982, Feb., 1998.


  88. C. Metra, M. Favalli, B. Ricco'
    Concurrent Checking of Clock Signal Correctness
    IEEE Design&Test of Computers
    pp. 42-48, Oct., 1998.

    Traditional concurrent-checking techniques may not detect the occurrence of the transient faults and resulting errors likely to affect clock signals in VLSI systems. The authors present a new method and slef-checking circuit implementation for concurrently checking the correctness of clock distribution network signals in synchronous systems.

  89. C. Metra, M. Favalli, B. Ricco'
    Signal Coding Technique and CMOS Gates for Strongly Fault-Secure Combinational Functional Blocks
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
    Austin (Texas), pp. 174-182, Nov., 1998.

    This paper proposes a signal coding technique (using frequency redundancy) and CMOS gates to allow the design of functional blocks of self-checking circuits whose correct operation is guaranteed with respect to a wide set of possible, internal faults. These include not only conventional stuck-ats, but also transistor stuck-ons, transistor stuck-opens and resistive bridgings. Compared to the alternative, existing solution, the technique proposed here does not imply any critical constraint on the circuit electrical parameters. Hence it is better suited to the design of next generation, deep submicron technology circuits.

  90. C. Metra, M. Favalli, B. Ricco'
    On-Line Detection of Logic Errors due to Crosstalk, Delay, and Transient Faults
    IEEE International Test Conference (ITC)
    Washington, DC (USA), pp. 524-533, Oct., 1998.

    This paper analyses the problem of systems' on-line testing with respect to logic errors due to crosstalk, delay and transient faults. In particular, we show that logic errors due to crosstalk noise between internal, adjacent lines may be not on-line detectable by conventional concurrent error detection techniques using error detecting codes. Hence, a detector is proposed that allows the on-line detection of such logic errors, and that is self-checking with respect to a wide set of possible internal faults representative of realistic failures, including crosstalk, delay, and transient faults.

  91. L. Benini, A. Bogliolo, M. Favalli, G. De Micheli
    Regression models for behavioral power estimation
    Integrated Computer-Aided Engineering
    vol. 5, pp. 95-106, Feb., 1998.


  92. C. Metra, M. Favalli, B. Ricco'
    Novel Implementation for Highly Testable Parity Code Checkers
    IEEE International On-Line Testing Workshop
    Capri (Italy), pp. 167-171, Jul., 1998.

    This paper proposes a novel CMOS implementation of single output, as well as two output, possibly embedded, parity code checkers, that are Totally Self-Checking or Strongly Code-Disjoint with respect to all possible internal node stuck-ats, transistor stuck-ons, transistor stuck-opens and resistive bridgings. These characteristics are not paid in terms of area overhead, speed and power consumption compared to more conventional solutions.

  93. Michele Favalli, Cecilia Metra
    On the design of self-checking functional units based on Shannon circuits
    IEEE Design and Test in Europe Conference (DATE)
    Munchen (Germany), pp. 368-375, Mar., 1999.

    This paper investigates the application of Shannon (BDD) circuits, that feature interesting low-power capabilities, to the design of self-checking functional units. A technique is proposed that, by using a time redundancy approach, makes this kind of circuits totally self-checking with respect to stuck-at faults. For a set of possibly used pass-transistor-based CMOS implementations, we show that the totally self-checking or the strongly fault secure properties hold for a wide r set of realistic faults, including transistors stuck-open/on and bridgings.

  94. Michele Favalli, Cecilia Metra
    Bus crosstalk fault detection capabilities of error detecting codes for on-line testing
    IEEE Transactions on VLSI Systems
    vol. 7, no. 3, pp. 392-396, Sep., 1999.

    This paper analyzes some of the most common error detecting codes used in self-checking circuits with respect to the errors induced by crosstalk faults. The electrical level behavior of circuits in the presence of crosstalk faults has been analyzed by considering these faults as parametric. A logic level model providing the probability of errors has been abstracted and applied to the case of functional unit outputs (buses). Finally, the probability of detectable and undetectable errors has been evaluated for the parity, two-rail, m-out-of-n and Berger codes, thus providing some design hint.

  95. C. Metra, R. Degiampietro, M. Favalli, B. Ricco'
    Concurrent Detection and Diagnosis Scheme for transient, Delay and Crosstalk Faults
    IEEE International On-Line Testing Workshop
    Rhodes, Greece, pp. 66-70, Jul., 1999.

    This paper presents a detection and diagnosis scheme for transient, delay and crosstalk faults possibly affecting data/address lines. Such a scheme is self-checking with respect to possible internal faults belonging to a realistic set, and can be implemented using VLSI, very deep submicron, as well as low-cost FPGAs.

  96. C. Metra, M. Favalli, B. Ricco'
    On-Line Testing and Diagnosis of Bus Lines with Respect to Intermediate Voltage Values
    IEEE Design and Test in Europe Conference (DATE)
    Paris (France), pp. 763-763, Mar., 2000.

    This paper presents a self-checking, on-line testing and diagnosis scheme for bus lines affected by intermediate voltage values possibly due to bridging faults, or to different kinds of faults affecting the bus connected units.

  97. C. Metra, M. Favalli, B. Ricco'
    On-Line Testing and Diagnosis Scheme for Intermediate Voltage Values Affecting Bus Lines
    IEEE International Defect Based Testing Workshop (DBT)
    Montreal (Canada), pp. 76-81, Apr., 2000.


  98. C. Metra, M. Favalli, B. Ricco'
    Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-Checking Circuits
    VLSI Design
    vol. 11-1, pp. 23-34, Jan., 2000.


  99. M. Favalli, C. Metra
    Bridging Faults in Pipelined Circuits
    Journal of Electronic Testing, Theory and Applications
    vol. 16-6, pp. 617-629, Dec., 2000.


  100. A. Bogliolo, M. Favalli, M. Damiani
    Enabling testability of fault-tolerant circuits by means of IDDQ-checkable voters
    IEEE Transactions on VLSI Systems
    vol. 8, no. 4, pp. 415-419, Aug., 2000.


  101. C. Metra, M. Favalli, B. Ricco'
    Self-Checking Detection and Diagnosis Scheme for Transient, Delay and Crosstalk Faults Affecting Bus Lines
    IEEE Transactions on Computers
    vol. 49, no. 3, pp. 560-574, Jun., 2000.


  102. M. Dalpasso, A. Bogliolo, L. Benini, M. Favalli
    Virtual Fault Simulation of Distributed IP-based Designs
    IEEE Design and Test in Europe Conference (DATE)
    Paris, pp. 99-103, Mar., 2000.


  103. M. Favalli, C. Metra
    Single output distributed two-rail checker with diagnosing capabilities for bus based self-checking architectures
    IEEE On-Line Testing Workshop
    Taormina (it), pp. 100-105, Jul., 2001.


  104. M. Favalli, C. Metra
    Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures
    IEEE International On-Line Testing Workshop
    Giardini Naxos-Taormina (Italy), pp. 100-105, Jul., 2001.


  105. M. Favalli, C. Metra
    Optimization of error detecting codes for the detection of crosstalk originated errors
    IEEE Design and Test in Europe Conference (DATE)
    Munchen (D), pp. 290-296, Mar., 2001.


  106. M. Favalli, C. Metra
    Online Testing Approach for Very Deep-Submicron ICs
    IEEE Design&Test of Computers
    vol., pp. 16-23, Mar., 2002.


  107. M. Favalli, M. Dalpasso
    Bridging fault modeling and simulation for deep submicron CMOS ICs
    IEEE Transactions on Computer Aided Design
    vol. 21, no. 8, pp. 941-953, Aug., 2002.


  108. C. Metra, M. Favalli, S. Di Francescantonio, B. Ricco'
    On-Chip Clock Faults' Detector
    Journal of Electronic Testing, Theory and Applications
    vol. 18-4, pp. 555-564, Aug., 2002.


  109. C. Metra, L. Schiano, M. Favalli, B. Ricco'
    Self-checking scheme for the on-line testing of power supply noise
    IEEE Design and Test in Europe Conference (DATE)
    Paris (Fr), pp. 832-836, Mar., 2002.


  110. M. Favalli, C. Metra
    Single Output Distribute Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures
    Journal of Electronic Testing, Theory and Applications
    vol. 18, pp. 273-283, Mar., 2002.

    This paper proposes a distributed two-rail checker architecture which is specifically targeted to self-checking bus-based systems. The architecture makes use of a single bus line to provide error indication. With respect to conventional two-rail checkers additional diagnosing capabilities are provided. The checker is totally-self-checking with respect to stuck-at faults. It features also good self-testing properties with respect to parametric faults, such as bridgings and delay faults.

  111. M. Favalli, C. Metra
    Problems due to open faults in the interconnections of self-checking data-paths
    IEEE Design and Test in Europe Conference (DATE)
    Paris (Fr), pp. 612-617, Apr., 2002.


  112. M. Dalpasso, M. Favalli
    An evolutionary approach to the design of on chip pseudorandom test generators
    IEEE Design and Test in Europe Conference (DATE)
    Paris (Fr), p. 1122, Apr., 2002.


  113. C. Metra, S. Di Francescantonio, M. Favalli, B. Ricco'
    Scan Flip-Flops with On-Line Testing Ability with respect to input Delay and Crosstalk Faults
    Microelectronics Journal
    vol. 34, n. 1, pp. 100-110, Jan., 2003.


  114. C. Metra, L. Schiano, M. Favalli
    Concurrent Detection of Power Supply Noise
    IEEE Transactions on Reliability
    vol. 52, No. 4, pp. 469-475, Dec., 2003.


  115. M. Favalli, C. Metra
    TMR Voting in the Presence of Crosstalk Faults at the Voter Inputs
    IEEE Transactions on Reliability
    Vol. 53, No. 3, pp. 342 - 348, Sep., 2004.


  116. M. Favalli
    "Victim gate" crosstalk fault model
    IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems
    Cannes (Fr), pp. 191 - 199, Oct., 2004.


  117. M. Favalli
    Annotated bit flip fault model
    IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems
    Cannes (Fr), pp. 191 - 199, Oct., 2004.


  118. M. Favalli
    A fuzzy model for path delay fault detection
    IEEE Transactions on VLSI Systems
    Vol. 11, No. 8, pp. 943 - 956, Aug., 2005.


  119. M. Favalli
    Diversity analysis in the presence of delay faults affecting duplex systems
    IEEE Transactions on Computers
    Volume 55, Issue 3, March 2006 Page(s):348 - 352

  120. M. Favalli and C. Metra
    Pulse propagation for the detection of small delay defects
    IEEE Designa Automation and Test in Europe (DATE), Nice, April 2007
    Pages. 1 - 6

  121. M. Favalli
    Delay fault detection problems in circuits featuring a low combinational depth
    IEEE Defect and Fault Tolerance Symposium in VLSI Systems (DFTS)
    Rome, September 2007, Page(s):170 - 178

  122. M. Favalli and M. Dalpasso
    High quality test vectors for bridging faults in the presence of IC's parameters variations
    IEEE Defect and Fault Tolerance Symposium in VLSI Systems (DFTS)
    Rome, September 2007, Page(s):448 - 457