Research

Research

The research interests of Michele Favalli are in the area of digital ICs design, simulation and testing and include:

Fault Simulation and Modeling

  • Fault simulation and modeling of unconventional faults in CMOS circuits
  • Gate and macro-gate level fault simulation techniques
  • Switch-Level fault simulation techniques
  • Modeling and simulation of break faults
  • Analysis of dynamic and probabilistic effects of bridging faults
  • Resistive bridging faults in BiCMOS circuits
  • Symbolic simulation of bridging faults
  • Fault simulation algorithms
  • Fault simulation and test generation algorithms for current testing in CMOS circuits

    • Design for Testability

  • Built-In Self-Test and Pseudorandom Testing
  • Signature analysis
  • Weighted pseudorandom test generation
  • Testability measures
  • Design for testability for CMOS circuits

    • Self-checking circuits

  • Functional units
  • Design rules for checkers and functional units
  • Shannon (BDD) based self-checking functional units
  • Analysis of error detection capabilities of error detecting codes with respect to crosstalk faults
  • Checkers
  • CMOS checkers for ( two-rail , 1/n , m/n , and Berger codes)
  • Checkers for delay faults
  • Checkers for delay, transient and crosstalk faults
  • Checkers for clock signals faults
  • Checkers for bus based architectures
  • Checkers for power supply noise

    • Fault tolerant circuits

  • Error recovery
  • Voters

    • Simulation oriented to low-power design of digital ICs

  • Switch-level algorithms for power estimate
  • Behavioral-level algorithms for power estimate
  • Glitch power dissipation in CMOS ICs

    • List of pubblications

    DEIS - University of Bologna, Italy / mfavalli@deis.unibo.it