| D.E.I.S. - UNIVERSITA' DI BOLOGNA |
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| Dipartimento di Elettronica, Informatica e Sistemistica |
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Ing. Francesco Poletti Publications |
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■ F.Poletti,
D.Bertozzi,
A.Bogliolo, and L.Benini.
Performance analysis of
arbitration policies for SoC communication architectures.
Journal of Design Automation for Embedded Systems, 8:189--210, June/September 2003. [DAES03] ■
F.Poletti, P.Marchal, D.Atienza,
Luca Benini, Francky Catthoor and Jose M. Mendias.
An Integrated Hardware/Software Approach For Run-Time Scratchpad Management. In Proceedings of the ACM/IEEE Design Automation Conference (DAC), pages 238 - 243, San Diego, June 2004. Nominated as Best Paper of Conference. [DAC04] ■
Mohammed Javed Absar, Francesco
Poletti, Pol Marchal, Francky Catthoor and Luca Benini.
Fast and Power-Efficient Dynamic Data-Layout with DMA-Capable Memories, In PARC 2004. [PARC04] ■
David Atienza, Stylianos
Mamagkakis, Francesco Poletti, Jose M.Mendias, Francky Catthoor, Luca
Benini.
Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems, In Integration, the VLSI Journal, September 2004 [INTEGRATION04] ■ F.Poletti,
A.Poggiali, P. Marchal.
Flexible hardware/software support for message passing on a distributed shared memory architecture. Design, Automation and Test in Europe, 2005. Proceedings 2005 Page(s):736 - 741 Vol. 2 [DATE 05] ■ L.
Benini, D. Bertozzi, A.
Guerri, M. Milano, F. Poletti.
"Measuring Efficiency and Executability of allocation and scheduling in Multi-Processor Systems-on-Chip" "Intelligenza Artificiale, Anno II, Volume 4" , to appear. ■ L.
Benini, D. Bertozzi, A.
Guerri, M. Milano, F. Poletti.
"Measuring Efficiency and Executability of allocation and scheduling in Multi-Processor Systems-on-Chip" in "Atti della Giornata di Lavoro: Analisi sperimentale e benchmark di algoritmi per l'Intelligenza Artificiale" (AIIA-RCRA05), Ferrara, Italy, Jun. 2005. |
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